remove unused flag

[oota-llvm.git] / lib / Target / PowerPC / PPCInstrFormats.td

diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td
index be0b262783ff11244ae46bc9e92b800292767a95..9ed4393ff80bc1d5178ad1941a0e66a74e3e1a3e 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/lib/Target/PowerPC/PPCInstrFormats.td
@@ -16,7 +16,6 @@ class I<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin>
   field bits<32> Inst;
 
   bit PPC64 = 0;  // Default value, override with isPPC64
-  bit VMX = 0;    // Default value, override with isVMX
 
   let Name = "";
   let Namespace = "PPC";
@@ -325,6 +324,43 @@ class XForm_28<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
   : XForm_base_r3xo<opcode, xo, OL, asmstr, itin, pattern> {
 }
 
+// DCB_Form - Form X instruction, used for dcb* instructions.
+class DCB_Form<bits<10> xo, bits<5> immfield, dag OL, string asmstr, 
+                      InstrItinClass itin, list<dag> pattern>
+  : I<31, OL, asmstr, itin> {
+  bits<5> A;
+  bits<5> B;
+
+  let Pattern = pattern;
+
+  let Inst{6-10}  = immfield;
+  let Inst{11-15} = A;
+  let Inst{16-20} = B;
+  let Inst{21-30} = xo;
+  let Inst{31}    = 0;
+}
+
+
+// DSS_Form - Form X instruction, used for altivec dss* instructions.
+class DSS_Form<bits<10> xo, dag OL, string asmstr, 
+                      InstrItinClass itin, list<dag> pattern>
+  : I<31, OL, asmstr, itin> {
+  bits<1> T;
+  bits<2> STRM;
+  bits<5> A;
+  bits<5> B;
+
+  let Pattern = pattern;
+
+  let Inst{6}     = T;
+  let Inst{7-8}   = 0;
+  let Inst{9-10}  = STRM;
+  let Inst{11-15} = A;
+  let Inst{16-20} = B;
+  let Inst{21-30} = xo;
+  let Inst{31}    = 0;
+}
+
 // 1.7.7 XL-Form
 class XLForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr,
                InstrItinClass itin>
@@ -589,12 +625,34 @@ class MDForm_1<bits<6> opcode, bits<3> xo, dag OL, string asmstr,
   let Inst{31}    = RC;
 }
 
+
+
 // E-1 VA-Form
+
+// VAForm_1 - DACB ordering.
 class VAForm_1<bits<6> xo, dag OL, string asmstr,
                InstrItinClass itin, list<dag> pattern>
     : I<4, OL, asmstr, itin> {
   bits<5> VD;
   bits<5> VA;
+  bits<5> VC;
+  bits<5> VB;
+
+  let Pattern = pattern;
+  
+  let Inst{6-10}  = VD;
+  let Inst{11-15} = VA;
+  let Inst{16-20} = VB;
+  let Inst{21-25} = VC;
+  let Inst{26-31} = xo;
+}
+
+// VAForm_1a - DABC ordering.
+class VAForm_1a<bits<6> xo, dag OL, string asmstr,
+                InstrItinClass itin, list<dag> pattern>
+    : I<4, OL, asmstr, itin> {
+  bits<5> VD;
+  bits<5> VA;
   bits<5> VB;
   bits<5> VC;
 
@@ -607,6 +665,24 @@ class VAForm_1<bits<6> xo, dag OL, string asmstr,
   let Inst{26-31} = xo;
 }
 
+class VAForm_2<bits<6> xo, dag OL, string asmstr,
+               InstrItinClass itin, list<dag> pattern>
+    : I<4, OL, asmstr, itin> {
+  bits<5> VD;
+  bits<5> VA;
+  bits<5> VB;
+  bits<4> SH;
+
+  let Pattern = pattern;
+  
+  let Inst{6-10}  = VD;
+  let Inst{11-15} = VA;
+  let Inst{16-20} = VB;
+  let Inst{21}    = 0;
+  let Inst{22-25} = SH;
+  let Inst{26-31} = xo;
+}
+
 // E-2 VX-Form
 class VXForm_1<bits<11> xo, dag OL, string asmstr,
                InstrItinClass itin, list<dag> pattern>
@@ -645,20 +721,63 @@ class VXForm_2<bits<11> xo, dag OL, string asmstr,
   let Inst{21-31} = xo;
 }
 
+class VXForm_3<bits<11> xo, dag OL, string asmstr,
+               InstrItinClass itin, list<dag> pattern>
+    : I<4, OL, asmstr, itin> {
+  bits<5> VD;
+  bits<5> IMM;
+  
+  let Pattern = pattern;
+  
+  let Inst{6-10}  = VD;
+  let Inst{11-15} = IMM;
+  let Inst{16-20} = 0;
+  let Inst{21-31} = xo;
+}
+
+/// VXForm_4 - VX instructions with "VD,0,0" register fields, like mfvscr.
+class VXForm_4<bits<11> xo, dag OL, string asmstr,
+               InstrItinClass itin, list<dag> pattern>
+    : I<4, OL, asmstr, itin> {
+  bits<5> VD;
+  
+  let Pattern = pattern;
+  
+  let Inst{6-10}  = VD;
+  let Inst{11-15} = 0;
+  let Inst{16-20} = 0;
+  let Inst{21-31} = xo;
+}
+
+/// VXForm_5 - VX instructions with "0,0,VB" register fields, like mtvscr.
+class VXForm_5<bits<11> xo, dag OL, string asmstr,
+               InstrItinClass itin, list<dag> pattern>
+    : I<4, OL, asmstr, itin> {
+  bits<5> VB;
+  
+  let Pattern = pattern;
+  
+  let Inst{6-10}  = 0;
+  let Inst{11-15} = 0;
+  let Inst{16-20} = VB;
+  let Inst{21-31} = xo;
+}
+
 // E-4 VXR-Form
-class VXRForm_1<bits<10> xo, bit rc, dag OL, string asmstr,
+class VXRForm_1<bits<10> xo, dag OL, string asmstr,
                InstrItinClass itin, list<dag> pattern>
     : I<4, OL, asmstr, itin> {
   bits<5> VD;
   bits<5> VA;
   bits<5> VB;
+  bit RC = 0;
   
   let Pattern = pattern;
   
   let Inst{6-10}  = VD;
   let Inst{11-15} = VA;
   let Inst{16-20} = VB;
-  let Inst{21}    = rc;
+  let Inst{21}    = RC;
   let Inst{22-31} = xo;
 }