#include "llvm/ADT/STLExtras.h"
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/Support/CommandLine.h"
+#include "llvm/Target/TargetAsmInfo.h"
using namespace llvm;
extern cl::opt<bool> EnablePPC32RS; // FIXME (64-bit): See PPCRegisterInfo.cpp.
case PPC::LWZ:
case PPC::LFS:
case PPC::LFD:
- if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
- MI->getOperand(2).isFI()) {
+ if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
+ MI->getOperand(2).isFrameIndex()) {
FrameIndex = MI->getOperand(2).getIndex();
return MI->getOperand(0).getReg();
}
case PPC::STW:
case PPC::STFS:
case PPC::STFD:
- if (MI->getOperand(1).isImm() && !MI->getOperand(1).getImm() &&
- MI->getOperand(2).isFI()) {
+ if (MI->getOperand(1).isImmediate() && !MI->getOperand(1).getImm() &&
+ MI->getOperand(2).isFrameIndex()) {
FrameIndex = MI->getOperand(2).getIndex();
return MI->getOperand(0).getReg();
}
// commuteInstruction - We can commute rlwimi instructions, but only if the
// rotate amt is zero. We also have to munge the immediates a bit.
-MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
+MachineInstr *
+PPCInstrInfo::commuteInstruction(MachineInstr *MI, bool NewMI) const {
+ MachineFunction &MF = *MI->getParent()->getParent();
+
// Normal instructions can be commuted the obvious way.
if (MI->getOpcode() != PPC::RLWIMI)
- return TargetInstrInfoImpl::commuteInstruction(MI);
+ return TargetInstrInfoImpl::commuteInstruction(MI, NewMI);
// Cannot commute if it has a non-zero rotate count.
if (MI->getOperand(3).getImm() != 0)
unsigned Reg2 = MI->getOperand(2).getReg();
bool Reg1IsKill = MI->getOperand(1).isKill();
bool Reg2IsKill = MI->getOperand(2).isKill();
+ bool ChangeReg0 = false;
// If machine instrs are no longer in two-address forms, update
// destination register as well.
if (Reg0 == Reg1) {
// Must be two address instruction!
assert(MI->getDesc().getOperandConstraint(0, TOI::TIED_TO) &&
"Expecting a two-address instruction!");
- MI->getOperand(0).setReg(Reg2);
Reg2IsKill = false;
+ ChangeReg0 = true;
+ }
+
+ // Masks.
+ unsigned MB = MI->getOperand(4).getImm();
+ unsigned ME = MI->getOperand(5).getImm();
+
+ if (NewMI) {
+ // Create a new instruction.
+ unsigned Reg0 = ChangeReg0 ? Reg2 : MI->getOperand(0).getReg();
+ bool Reg0IsDead = MI->getOperand(0).isDead();
+ return BuildMI(MF, MI->getDesc())
+ .addReg(Reg0, true, false, false, Reg0IsDead)
+ .addReg(Reg2, false, false, Reg2IsKill)
+ .addReg(Reg1, false, false, Reg1IsKill)
+ .addImm((ME+1) & 31)
+ .addImm((MB-1) & 31);
}
+
+ if (ChangeReg0)
+ MI->getOperand(0).setReg(Reg2);
MI->getOperand(2).setReg(Reg1);
MI->getOperand(1).setReg(Reg2);
MI->getOperand(2).setIsKill(Reg1IsKill);
MI->getOperand(1).setIsKill(Reg2IsKill);
// Swap the mask around.
- unsigned MB = MI->getOperand(4).getImm();
- unsigned ME = MI->getOperand(5).getImm();
MI->getOperand(4).setImm((ME+1) & 31);
MI->getOperand(5).setImm((MB-1) & 31);
return MI;
// Branch analysis.
bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
MachineBasicBlock *&FBB,
- std::vector<MachineOperand> &Cond) const {
+ SmallVectorImpl<MachineOperand> &Cond) const {
// If the block has no terminators, it just falls into the block after it.
MachineBasicBlock::iterator I = MBB.end();
if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
unsigned
PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
MachineBasicBlock *FBB,
- const std::vector<MachineOperand> &Cond) const {
+ const SmallVectorImpl<MachineOperand> &Cond) const {
// Shouldn't be a fall through.
assert(TBB && "InsertBranch must not be told to insert a fallthrough");
assert((Cond.size() == 2 || Cond.size() == 0) &&
return 2;
}
-void PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
+bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,
unsigned DestReg, unsigned SrcReg,
const TargetRegisterClass *DestRC,
const TargetRegisterClass *SrcRC) const {
if (DestRC != SrcRC) {
- cerr << "Not yet supported!";
- abort();
+ // Not yet supported!
+ return false;
}
if (DestRC == PPC::GPRCRegisterClass) {
} else if (DestRC == PPC::CRBITRCRegisterClass) {
BuildMI(MBB, MI, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
} else {
- cerr << "Attempt to copy register that is not GPR or FPR";
- abort();
+ // Attempt to copy register that is not GPR or FPR
+ return false;
}
+
+ return true;
}
bool
-PPCInstrInfo::StoreRegToStackSlot(unsigned SrcReg, bool isKill,
+PPCInstrInfo::StoreRegToStackSlot(MachineFunction &MF,
+ unsigned SrcReg, bool isKill,
int FrameIdx,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const{
if (RC == PPC::GPRCRegisterClass) {
if (SrcReg != PPC::LR) {
- NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STW))
+ NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
.addReg(SrcReg, false, false, isKill),
FrameIdx));
} else {
// FIXME: this spills LR immediately to memory in one step. To do this,
// we use R11, which we know cannot be used in the prolog/epilog. This is
// a hack.
- NewMIs.push_back(BuildMI(get(PPC::MFLR), PPC::R11));
- NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STW))
+ NewMIs.push_back(BuildMI(MF, get(PPC::MFLR), PPC::R11));
+ NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
.addReg(PPC::R11, false, false, isKill),
FrameIdx));
}
} else if (RC == PPC::G8RCRegisterClass) {
if (SrcReg != PPC::LR8) {
- NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STD))
+ NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD))
.addReg(SrcReg, false, false, isKill), FrameIdx));
} else {
// FIXME: this spills LR immediately to memory in one step. To do this,
// we use R11, which we know cannot be used in the prolog/epilog. This is
// a hack.
- NewMIs.push_back(BuildMI(get(PPC::MFLR8), PPC::X11));
- NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STD))
+ NewMIs.push_back(BuildMI(MF, get(PPC::MFLR8), PPC::X11));
+ NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STD))
.addReg(PPC::X11, false, false, isKill), FrameIdx));
}
} else if (RC == PPC::F8RCRegisterClass) {
- NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STFD))
+ NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFD))
.addReg(SrcReg, false, false, isKill), FrameIdx));
} else if (RC == PPC::F4RCRegisterClass) {
- NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STFS))
+ NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STFS))
.addReg(SrcReg, false, false, isKill), FrameIdx));
} else if (RC == PPC::CRRCRegisterClass) {
if ((EnablePPC32RS && !TM.getSubtargetImpl()->isPPC64()) ||
(EnablePPC64RS && TM.getSubtargetImpl()->isPPC64())) {
// FIXME (64-bit): Enable
- NewMIs.push_back(addFrameReference(BuildMI(get(PPC::SPILL_CR))
+ NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::SPILL_CR))
.addReg(SrcReg, false, false, isKill),
- FrameIdx));
+ FrameIdx));
return true;
} else {
// FIXME: We use R0 here, because it isn't available for RA. We need to
// store the CR in the low 4-bits of the saved value. First, issue a MFCR
// to save all of the CRBits.
- NewMIs.push_back(BuildMI(get(PPC::MFCR), PPC::R0));
+ NewMIs.push_back(BuildMI(MF, get(PPC::MFCR), PPC::R0));
// If the saved register wasn't CR0, shift the bits left so that they are
// in CR0's slot.
if (SrcReg != PPC::CR0) {
unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(SrcReg)*4;
// rlwinm r0, r0, ShiftBits, 0, 31.
- NewMIs.push_back(BuildMI(get(PPC::RLWINM), PPC::R0)
+ NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0)
.addReg(PPC::R0).addImm(ShiftBits).addImm(0).addImm(31));
}
- NewMIs.push_back(addFrameReference(BuildMI(get(PPC::STW))
+ NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::STW))
.addReg(PPC::R0, false, false, isKill),
FrameIdx));
}
else if (SrcReg >= PPC::CR7LT || SrcReg <= PPC::CR7UN)
Reg = PPC::CR7;
- return StoreRegToStackSlot(Reg, isKill, FrameIdx,
+ return StoreRegToStackSlot(MF, Reg, isKill, FrameIdx,
PPC::CRRCRegisterClass, NewMIs);
} else if (RC == PPC::VRRCRegisterClass) {
// STVX VAL, 0, R0
//
// FIXME: We use R0 here, because it isn't available for RA.
- NewMIs.push_back(addFrameReference(BuildMI(get(PPC::ADDI), PPC::R0),
+ NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0),
FrameIdx, 0, 0));
- NewMIs.push_back(BuildMI(get(PPC::STVX))
+ NewMIs.push_back(BuildMI(MF, get(PPC::STVX))
.addReg(SrcReg, false, false, isKill).addReg(PPC::R0).addReg(PPC::R0));
} else {
assert(0 && "Unknown regclass!");
MachineBasicBlock::iterator MI,
unsigned SrcReg, bool isKill, int FrameIdx,
const TargetRegisterClass *RC) const {
+ MachineFunction &MF = *MBB.getParent();
SmallVector<MachineInstr*, 4> NewMIs;
- if (StoreRegToStackSlot(SrcReg, isKill, FrameIdx, RC, NewMIs)) {
- PPCFunctionInfo *FuncInfo = M
BB.getParent()->getInfo<PPCFunctionInfo>();
+ if (StoreRegToStackSlot(MF, SrcReg, isKill, FrameIdx, RC, NewMIs)) {
+ PPCFunctionInfo *FuncInfo = M
F.getInfo<PPCFunctionInfo>();
FuncInfo->setSpillsCR();
}
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs) const{
if (Addr[0].isFrameIndex()) {
- if (StoreRegToStackSlot(SrcReg, isKill, Addr[0].getIndex(), RC, NewMIs)) {
+ if (StoreRegToStackSlot(MF, SrcReg, isKill,
+ Addr[0].getIndex(), RC, NewMIs)) {
PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
FuncInfo->setSpillsCR();
}
assert(0 && "Unknown regclass!");
abort();
}
- MachineInstrBuilder MIB = BuildMI(get(Opc))
+ MachineInstrBuilder MIB = BuildMI(MF, get(Opc))
.addReg(SrcReg, false, false, isKill);
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
}
void
-PPCInstrInfo::LoadRegFromStackSlot(unsigned DestReg, int FrameIdx,
+PPCInstrInfo::LoadRegFromStackSlot(MachineFunction &MF,
+ unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs)const{
if (RC == PPC::GPRCRegisterClass) {
if (DestReg != PPC::LR) {
- NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LWZ), DestReg),
+ NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), DestReg),
FrameIdx));
} else {
- NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LWZ), PPC::R11),
+ NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R11),
FrameIdx));
- NewMIs.push_back(BuildMI(get(PPC::MTLR)).addReg(PPC::R11));
+ NewMIs.push_back(BuildMI(MF, get(PPC::MTLR)).addReg(PPC::R11));
}
} else if (RC == PPC::G8RCRegisterClass) {
if (DestReg != PPC::LR8) {
- NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LD), DestReg),
+ NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), DestReg),
FrameIdx));
} else {
- NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LD), PPC::R11),
+ NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LD), PPC::R11),
FrameIdx));
- NewMIs.push_back(BuildMI(get(PPC::MTLR8)).addReg(PPC::R11));
+ NewMIs.push_back(BuildMI(MF, get(PPC::MTLR8)).addReg(PPC::R11));
}
} else if (RC == PPC::F8RCRegisterClass) {
- NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LFD), DestReg),
+ NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFD), DestReg),
FrameIdx));
} else if (RC == PPC::F4RCRegisterClass) {
- NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LFS), DestReg),
+ NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LFS), DestReg),
FrameIdx));
} else if (RC == PPC::CRRCRegisterClass) {
// FIXME: We use R0 here, because it isn't available for RA.
- NewMIs.push_back(addFrameReference(BuildMI(get(PPC::LWZ), PPC::R0),
+ NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::LWZ), PPC::R0),
FrameIdx));
// If the reloaded register isn't CR0, shift the bits right so that they are
if (DestReg != PPC::CR0) {
unsigned ShiftBits = PPCRegisterInfo::getRegisterNumbering(DestReg)*4;
// rlwinm r11, r11, 32-ShiftBits, 0, 31.
- NewMIs.push_back(BuildMI(get(PPC::RLWINM), PPC::R0)
+ NewMIs.push_back(BuildMI(MF, get(PPC::RLWINM), PPC::R0)
.addReg(PPC::R0).addImm(32-ShiftBits).addImm(0).addImm(31));
}
- NewMIs.push_back(BuildMI(get(PPC::MTCRF), DestReg).addReg(PPC::R0));
+ NewMIs.push_back(BuildMI(MF, get(PPC::MTCRF), DestReg).addReg(PPC::R0));
} else if (RC == PPC::CRBITRCRegisterClass) {
unsigned Reg = 0;
else if (DestReg >= PPC::CR7LT || DestReg <= PPC::CR7UN)
Reg = PPC::CR7;
- return LoadRegFromStackSlot(Reg, FrameIdx,
+ return LoadRegFromStackSlot(MF, Reg, FrameIdx,
PPC::CRRCRegisterClass, NewMIs);
} else if (RC == PPC::VRRCRegisterClass) {
// Dest = LVX 0, R0
//
// FIXME: We use R0 here, because it isn't available for RA.
- NewMIs.push_back(addFrameReference(BuildMI(get(PPC::ADDI), PPC::R0),
+ NewMIs.push_back(addFrameReference(BuildMI(MF, get(PPC::ADDI), PPC::R0),
FrameIdx, 0, 0));
- NewMIs.push_back(BuildMI(get(PPC::LVX),DestReg).addReg(PPC::R0)
+ NewMIs.push_back(BuildMI(MF, get(PPC::LVX),DestReg).addReg(PPC::R0)
.addReg(PPC::R0));
} else {
assert(0 && "Unknown regclass!");
MachineBasicBlock::iterator MI,
unsigned DestReg, int FrameIdx,
const TargetRegisterClass *RC) const {
+ MachineFunction &MF = *MBB.getParent();
SmallVector<MachineInstr*, 4> NewMIs;
- LoadRegFromStackSlot(DestReg, FrameIdx, RC, NewMIs);
+ LoadRegFromStackSlot(MF, DestReg, FrameIdx, RC, NewMIs);
for (unsigned i = 0, e = NewMIs.size(); i != e; ++i)
MBB.insert(MI, NewMIs[i]);
}
const TargetRegisterClass *RC,
SmallVectorImpl<MachineInstr*> &NewMIs)const{
if (Addr[0].isFrameIndex()) {
- LoadRegFromStackSlot(DestReg, Addr[0].getIndex(), RC, NewMIs);
+ LoadRegFromStackSlot(MF, DestReg, Addr[0].getIndex(), RC, NewMIs);
return;
}
assert(0 && "Unknown regclass!");
abort();
}
- MachineInstrBuilder MIB = BuildMI(get(Opc), DestReg);
+ MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
MachineOperand &MO = Addr[i];
if (MO.isRegister())
MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
- NewMI = addFrameReference(BuildMI(get(PPC::STW)).addReg(InReg),
+ bool isKill = MI->getOperand(1).isKill();
+ NewMI = addFrameReference(BuildMI(MF, get(PPC::STW))
+ .addReg(InReg, false, false, isKill),
FrameIndex);
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
- NewMI = addFrameReference(BuildMI(get(PPC::LWZ), OutReg),
+ bool isDead = MI->getOperand(0).isDead();
+ NewMI = addFrameReference(BuildMI(MF, get(PPC::LWZ))
+ .addReg(OutReg, true, false, false, isDead),
FrameIndex);
}
} else if ((Opc == PPC::OR8 &&
MI->getOperand(1).getReg() == MI->getOperand(2).getReg())) {
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
- NewMI = addFrameReference(BuildMI(get(PPC::STD)).addReg(InReg),
+ bool isKill = MI->getOperand(1).isKill();
+ NewMI = addFrameReference(BuildMI(MF, get(PPC::STD))
+ .addReg(InReg, false, false, isKill),
FrameIndex);
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
- NewMI = addFrameReference(BuildMI(get(PPC::LD), OutReg), FrameIndex);
+ bool isDead = MI->getOperand(0).isDead();
+ NewMI = addFrameReference(BuildMI(MF, get(PPC::LD))
+ .addReg(OutReg, true, false, false, isDead),
+ FrameIndex);
}
} else if (Opc == PPC::FMRD) {
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
- NewMI = addFrameReference(BuildMI(get(PPC::STFD)).addReg(InReg),
+ bool isKill = MI->getOperand(1).isKill();
+ NewMI = addFrameReference(BuildMI(MF, get(PPC::STFD))
+ .addReg(InReg, false, false, isKill),
FrameIndex);
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
- NewMI = addFrameReference(BuildMI(get(PPC::LFD), OutReg), FrameIndex);
+ bool isDead = MI->getOperand(0).isDead();
+ NewMI = addFrameReference(BuildMI(MF, get(PPC::LFD))
+ .addReg(OutReg, true, false, false, isDead),
+ FrameIndex);
}
} else if (Opc == PPC::FMRS) {
if (OpNum == 0) { // move -> store
unsigned InReg = MI->getOperand(1).getReg();
- NewMI = addFrameReference(BuildMI(get(PPC::STFS)).addReg(InReg),
+ bool isKill = MI->getOperand(1).isKill();
+ NewMI = addFrameReference(BuildMI(MF, get(PPC::STFS))
+ .addReg(InReg, false, false, isKill),
FrameIndex);
} else { // move -> load
unsigned OutReg = MI->getOperand(0).getReg();
- NewMI = addFrameReference(BuildMI(get(PPC::LFS), OutReg), FrameIndex);
+ bool isDead = MI->getOperand(0).isDead();
+ NewMI = addFrameReference(BuildMI(MF, get(PPC::LFS))
+ .addReg(OutReg, true, false, false, isDead),
+ FrameIndex);
}
}
- if (NewMI)
- NewMI->copyKillDeadInfo(MI);
return NewMI;
}
}
bool PPCInstrInfo::
-ReverseBranchCondition(std::vector<MachineOperand> &Cond) const {
+ReverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const {
assert(Cond.size() == 2 && "Invalid PPC branch opcode!");
// Leave the CR# the same, but invert the condition.
Cond[0].setImm(PPC::InvertPredicate((PPC::Predicate)Cond[0].getImm()));
return false;
}
+
+/// GetInstSize - Return the number of bytes of code the specified
+/// instruction may be. This returns the maximum number of bytes.
+///
+unsigned PPCInstrInfo::GetInstSizeInBytes(const MachineInstr *MI) const {
+ switch (MI->getOpcode()) {
+ case PPC::INLINEASM: { // Inline Asm: Variable size.
+ const MachineFunction *MF = MI->getParent()->getParent();
+ const char *AsmStr = MI->getOperand(0).getSymbolName();
+ return MF->getTarget().getTargetAsmInfo()->getInlineAsmLength(AsmStr);
+ }
+ case PPC::DBG_LABEL:
+ case PPC::EH_LABEL:
+ case PPC::GC_LABEL:
+ return 0;
+ default:
+ return 4; // PowerPC instructions are all 4 bytes
+ }
+}
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