Function temporaries can not overlap with retval or args.See the comment in source...

[oota-llvm.git] / lib / Target / PowerPC / PPCInstrInfo.cpp

diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index 674b36c5a38e9c4f6090339143b1003edb9eed38..3e0c7e73ac34d836789d908bf4abc295b45103fc 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -30,26 +30,20 @@ PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
   : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
     RI(*TM.getSubtargetImpl(), *this) {}
 
-/// getPointerRegClass - Return the register class to use to hold pointers.
-/// This is used for addressing modes.
-const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
-  if (TM.getSubtargetImpl()->isPPC64())
-    return &PPC::G8RCRegClass;
-  else
-    return &PPC::GPRCRegClass;
-}
-
-
 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
                                unsigned& sourceReg,
-                               unsigned& destReg) const {
+                               unsigned& destReg,
+                               unsigned& sourceSubIdx,
+                               unsigned& destSubIdx) const {
+  sourceSubIdx = destSubIdx = 0; // No sub-registers.
+
   unsigned oc = MI.getOpcode();
   if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
       oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
     assert(MI.getNumOperands() >= 3 &&
-           MI.getOperand(0).isRegister() &&
-           MI.getOperand(1).isRegister() &&
-           MI.getOperand(2).isRegister() &&
+           MI.getOperand(0).isReg() &&
+           MI.getOperand(1).isReg() &&
+           MI.getOperand(2).isReg() &&
            "invalid PPC OR instruction!");
     if (MI.getOperand(1).getReg() == MI.getOperand(2).getReg()) {
       sourceReg = MI.getOperand(1).getReg();
@@ -58,19 +52,19 @@ bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
     }
   } else if (oc == PPC::ADDI) {             // addi r1, r2, 0
     assert(MI.getNumOperands() >= 3 &&
-           MI.getOperand(0).isRegister() &&
-           MI.getOperand(2).isImmediate() &&
+           MI.getOperand(0).isReg() &&
+           MI.getOperand(2).isImm() &&
            "invalid PPC ADDI instruction!");
-    if (MI.getOperand(1).isRegister() && MI.getOperand(2).getImm() == 0) {
+    if (MI.getOperand(1).isReg() && MI.getOperand(2).getImm() == 0) {
       sourceReg = MI.getOperand(1).getReg();
       destReg = MI.getOperand(0).getReg();
       return true;
     }
   } else if (oc == PPC::ORI) {             // ori r1, r2, 0
     assert(MI.getNumOperands() >= 3 &&
-           MI.getOperand(0).isRegister() &&
-           MI.getOperand(1).isRegister() &&
-           MI.getOperand(2).isImmediate() &&
+           MI.getOperand(0).isReg() &&
+           MI.getOperand(1).isReg() &&
+           MI.getOperand(2).isImm() &&
            "invalid PPC ORI instruction!");
     if (MI.getOperand(2).getImm() == 0) {
       sourceReg = MI.getOperand(1).getReg();
@@ -80,16 +74,16 @@ bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
   } else if (oc == PPC::FMRS || oc == PPC::FMRD ||
              oc == PPC::FMRSD) {      // fmr r1, r2
     assert(MI.getNumOperands() >= 2 &&
-           MI.getOperand(0).isRegister() &&
-           MI.getOperand(1).isRegister() &&
+           MI.getOperand(0).isReg() &&
+           MI.getOperand(1).isReg() &&
            "invalid PPC FMR instruction");
     sourceReg = MI.getOperand(1).getReg();
     destReg = MI.getOperand(0).getReg();
     return true;
   } else if (oc == PPC::MCRF) {             // mcrf cr1, cr2
     assert(MI.getNumOperands() >= 2 &&
-           MI.getOperand(0).isRegister() &&
-           MI.getOperand(1).isRegister() &&
+           MI.getOperand(0).isReg() &&
+           MI.getOperand(1).isReg() &&
            "invalid PPC MCRF instruction");
     sourceReg = MI.getOperand(1).getReg();
     destReg = MI.getOperand(0).getReg();
@@ -98,7 +92,7 @@ bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
   return false;
 }
 
-unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI, 
+unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 
                                            int &FrameIndex) const {
   switch (MI->getOpcode()) {
   default: break;
@@ -116,7 +110,7 @@ unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
   return 0;
 }
 
-unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI, 
+unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 
                                           int &FrameIndex) const {
   switch (MI->getOpcode()) {
   default: break;
@@ -210,7 +204,8 @@ void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
 // Branch analysis.
 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
                                  MachineBasicBlock *&FBB,
-                                 SmallVectorImpl<MachineOperand> &Cond) const {
+                                 SmallVectorImpl<MachineOperand> &Cond,
+                                 bool AllowModify) const {
   // If the block has no terminators, it just falls into the block after it.
   MachineBasicBlock::iterator I = MBB.end();
   if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
@@ -259,7 +254,8 @@ bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
       LastInst->getOpcode() == PPC::B) {
     TBB = SecondLastInst->getOperand(0).getMBB();
     I = LastInst;
-    I->eraseFromParent();
+    if (AllowModify)
+      I->eraseFromParent();
     return false;
   }
 
@@ -315,14 +311,14 @@ PPCInstrInfo::InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
   return 2;
 }
 
-void PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
+bool PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator MI,
                                    unsigned DestReg, unsigned SrcReg,
                                    const TargetRegisterClass *DestRC,
                                    const TargetRegisterClass *SrcRC) const {
   if (DestRC != SrcRC) {
-    cerr << "Not yet supported!";
-    abort();
+    // Not yet supported!
+    return false;
   }
 
   if (DestRC == PPC::GPRCRegisterClass) {
@@ -340,9 +336,11 @@ void PPCInstrInfo::copyRegToReg(MachineBasicBlock &MBB,
   } else if (DestRC == PPC::CRBITRCRegisterClass) {
     BuildMI(MBB, MI, get(PPC::CROR), DestReg).addReg(SrcReg).addReg(SrcReg);
   } else {
-    cerr << "Attempt to copy register that is not GPR or FPR";
-    abort();
+    // Attempt to copy register that is not GPR or FPR
+    return false;
   }
+  
+  return true;
 }
 
 bool
@@ -476,7 +474,7 @@ void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
                                   SmallVectorImpl<MachineOperand> &Addr,
                                   const TargetRegisterClass *RC,
                                   SmallVectorImpl<MachineInstr*> &NewMIs) const{
-  if (Addr[0].isFrameIndex()) {
+  if (Addr[0].isFI()) {
     if (StoreRegToStackSlot(MF, SrcReg, isKill,
                             Addr[0].getIndex(), RC, NewMIs)) {
       PPCFunctionInfo *FuncInfo = MF.getInfo<PPCFunctionInfo>();
@@ -505,9 +503,9 @@ void PPCInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
     .addReg(SrcReg, false, false, isKill);
   for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
     MachineOperand &MO = Addr[i];
-    if (MO.isRegister())
+    if (MO.isReg())
       MIB.addReg(MO.getReg());
-    else if (MO.isImmediate())
+    else if (MO.isImm())
       MIB.addImm(MO.getImm());
     else
       MIB.addFrameIndex(MO.getIndex());
@@ -615,7 +613,7 @@ void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
                                    SmallVectorImpl<MachineOperand> &Addr,
                                    const TargetRegisterClass *RC,
                                    SmallVectorImpl<MachineInstr*> &NewMIs)const{
-  if (Addr[0].isFrameIndex()) {
+  if (Addr[0].isFI()) {
     LoadRegFromStackSlot(MF, DestReg, Addr[0].getIndex(), RC, NewMIs);
     return;
   }
@@ -640,9 +638,9 @@ void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
   MachineInstrBuilder MIB = BuildMI(MF, get(Opc), DestReg);
   for (unsigned i = 0, e = Addr.size(); i != e; ++i) {
     MachineOperand &MO = Addr[i];
-    if (MO.isRegister())
+    if (MO.isReg())
       MIB.addReg(MO.getReg());
-    else if (MO.isImmediate())
+    else if (MO.isImm())
       MIB.addImm(MO.getImm());
     else
       MIB.addFrameIndex(MO.getIndex());
@@ -653,10 +651,10 @@ void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
 
 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
 /// copy instructions, turning them into load/store instructions.
-MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineFunction &MF,
-                                              MachineInstr *MI,
-                                              SmallVectorImpl<unsigned> &Ops,
-                                              int FrameIndex) const {
+MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
+                                                  MachineInstr *MI,
+                                           const SmallVectorImpl<unsigned> &Ops,
+                                                  int FrameIndex) const {
   if (Ops.size() != 1) return NULL;
 
   // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
@@ -728,8 +726,8 @@ MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineFunction &MF,
   return NewMI;
 }
 
-bool PPCInstrInfo::canFoldMemoryOperand(MachineInstr *MI,
-                                        SmallVectorImpl<unsigned> &Ops) const {
+bool PPCInstrInfo::canFoldMemoryOperand(const MachineInstr *MI,
+                                  const SmallVectorImpl<unsigned> &Ops) const {
   if (Ops.size() != 1) return false;
 
   // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because
@@ -749,7 +747,7 @@ bool PPCInstrInfo::canFoldMemoryOperand(MachineInstr *MI,
 }
 
 
-bool PPCInstrInfo::BlockHasNoFallThrough(MachineBasicBlock &MBB) const {
+bool PPCInstrInfo::BlockHasNoFallThrough(const MachineBasicBlock &MBB) const {
   if (MBB.empty()) return false;
   
   switch (MBB.back().getOpcode()) {