Function temporaries can not overlap with retval or args.See the comment in source...

[oota-llvm.git] / lib / Target / PowerPC / PPCInstrInfo.cpp

diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index c2756685a40ed1ccce50da18087e96065ea8ac78..3e0c7e73ac34d836789d908bf4abc295b45103fc 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -30,19 +30,13 @@ PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
   : TargetInstrInfoImpl(PPCInsts, array_lengthof(PPCInsts)), TM(tm),
     RI(*TM.getSubtargetImpl(), *this) {}
 
-/// getPointerRegClass - Return the register class to use to hold pointers.
-/// This is used for addressing modes.
-const TargetRegisterClass *PPCInstrInfo::getPointerRegClass() const {
-  if (TM.getSubtargetImpl()->isPPC64())
-    return &PPC::G8RCRegClass;
-  else
-    return &PPC::GPRCRegClass;
-}
-
-
 bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
                                unsigned& sourceReg,
-                               unsigned& destReg) const {
+                               unsigned& destReg,
+                               unsigned& sourceSubIdx,
+                               unsigned& destSubIdx) const {
+  sourceSubIdx = destSubIdx = 0; // No sub-registers.
+
   unsigned oc = MI.getOpcode();
   if (oc == PPC::OR || oc == PPC::OR8 || oc == PPC::VOR ||
       oc == PPC::OR4To8 || oc == PPC::OR8To4) {                // or r1, r2, r2
@@ -98,7 +92,7 @@ bool PPCInstrInfo::isMoveInstr(const MachineInstr& MI,
   return false;
 }
 
-unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI, 
+unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI, 
                                            int &FrameIndex) const {
   switch (MI->getOpcode()) {
   default: break;
@@ -116,7 +110,7 @@ unsigned PPCInstrInfo::isLoadFromStackSlot(MachineInstr *MI,
   return 0;
 }
 
-unsigned PPCInstrInfo::isStoreToStackSlot(MachineInstr *MI, 
+unsigned PPCInstrInfo::isStoreToStackSlot(const MachineInstr *MI, 
                                           int &FrameIndex) const {
   switch (MI->getOpcode()) {
   default: break;
@@ -210,7 +204,8 @@ void PPCInstrInfo::insertNoop(MachineBasicBlock &MBB,
 // Branch analysis.
 bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
                                  MachineBasicBlock *&FBB,
-                                 SmallVectorImpl<MachineOperand> &Cond) const {
+                                 SmallVectorImpl<MachineOperand> &Cond,
+                                 bool AllowModify) const {
   // If the block has no terminators, it just falls into the block after it.
   MachineBasicBlock::iterator I = MBB.end();
   if (I == MBB.begin() || !isUnpredicatedTerminator(--I))
@@ -259,7 +254,8 @@ bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
       LastInst->getOpcode() == PPC::B) {
     TBB = SecondLastInst->getOperand(0).getMBB();
     I = LastInst;
-    I->eraseFromParent();
+    if (AllowModify)
+      I->eraseFromParent();
     return false;
   }
 
@@ -655,10 +651,10 @@ void PPCInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
 
 /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
 /// copy instructions, turning them into load/store instructions.
-MachineInstr *PPCInstrInfo::foldMemoryOperand(MachineFunction &MF,
-                                              MachineInstr *MI,
-                                              const SmallVectorImpl<unsigned> &Ops,
-                                              int FrameIndex) const {
+MachineInstr *PPCInstrInfo::foldMemoryOperandImpl(MachineFunction &MF,
+                                                  MachineInstr *MI,
+                                           const SmallVectorImpl<unsigned> &Ops,
+                                                  int FrameIndex) const {
   if (Ops.size() != 1) return NULL;
 
   // Make sure this is a reg-reg copy.  Note that we can't handle MCRF, because