Treat TargetGlobalAddress as a constant for the purpose of matching pre-inc stores...

[oota-llvm.git] / lib / Target / PowerPC / PPCInstrInfo.cpp

diff --git a/lib/Target/PowerPC/PPCInstrInfo.cpp b/lib/Target/PowerPC/PPCInstrInfo.cpp
index 8b868e69ecaa489d635831db7d410ce3843fff11..47f09dca77d31e6711c5b1a13b0e6064add69367 100644 (file)
--- a/lib/Target/PowerPC/PPCInstrInfo.cpp
+++ b/lib/Target/PowerPC/PPCInstrInfo.cpp
@@ -41,8 +41,8 @@ extern cl::opt<bool> DisablePPC64RS;
 using namespace llvm;
 
 static cl::
-opt<bool> EnableCTRLoopAnal("enable-ppc-ctrloop-analysis", cl::Hidden,
-            cl::desc("Enable analysis for CTR loops (experimental)"));
+opt<bool> DisableCTRLoopAnal("disable-ppc-ctrloop-analysis", cl::Hidden,
+            cl::desc("Disable analysis for CTR loops"));
 
 PPCInstrInfo::PPCInstrInfo(PPCTargetMachine &tm)
   : PPCGenInstrInfo(PPC::ADJCALLSTACKDOWN, PPC::ADJCALLSTACKUP),
@@ -79,6 +79,22 @@ ScheduleHazardRecognizer *PPCInstrInfo::CreateTargetPostRAHazardRecognizer(
 
   return new PPCScoreboardHazardRecognizer(II, DAG);
 }
+
+// Detect 32 -> 64-bit extensions where we may reuse the low sub-register.
+bool PPCInstrInfo::isCoalescableExtInstr(const MachineInstr &MI,
+                                         unsigned &SrcReg, unsigned &DstReg,
+                                         unsigned &SubIdx) const {
+  switch (MI.getOpcode()) {
+  default: return false;
+  case PPC::EXTSW:
+  case PPC::EXTSW_32_64:
+    SrcReg = MI.getOperand(1).getReg();
+    DstReg = MI.getOperand(0).getReg();
+    SubIdx = PPC::sub_32;
+    return true;
+  }
+}
+
 unsigned PPCInstrInfo::isLoadFromStackSlot(const MachineInstr *MI,
                                            int &FrameIndex) const {
   switch (MI->getOpcode()) {
@@ -233,7 +249,7 @@ bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
                LastInst->getOpcode() == PPC::BDNZ) {
       if (!LastInst->getOperand(0).isMBB())
         return true;
-      if (!EnableCTRLoopAnal)
+      if (DisableCTRLoopAnal)
         return true;
       TBB = LastInst->getOperand(0).getMBB();
       Cond.push_back(MachineOperand::CreateImm(1));
@@ -244,7 +260,7 @@ bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
                LastInst->getOpcode() == PPC::BDZ) {
       if (!LastInst->getOperand(0).isMBB())
         return true;
-      if (!EnableCTRLoopAnal)
+      if (DisableCTRLoopAnal)
         return true;
       TBB = LastInst->getOperand(0).getMBB();
       Cond.push_back(MachineOperand::CreateImm(0));
@@ -282,7 +298,7 @@ bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
     if (!SecondLastInst->getOperand(0).isMBB() ||
         !LastInst->getOperand(0).isMBB())
       return true;
-    if (!EnableCTRLoopAnal)
+    if (DisableCTRLoopAnal)
       return true;
     TBB = SecondLastInst->getOperand(0).getMBB();
     Cond.push_back(MachineOperand::CreateImm(1));
@@ -296,7 +312,7 @@ bool PPCInstrInfo::AnalyzeBranch(MachineBasicBlock &MBB,MachineBasicBlock *&TBB,
     if (!SecondLastInst->getOperand(0).isMBB() ||
         !LastInst->getOperand(0).isMBB())
       return true;
-    if (!EnableCTRLoopAnal)
+    if (DisableCTRLoopAnal)
       return true;
     TBB = SecondLastInst->getOperand(0).getMBB();
     Cond.push_back(MachineOperand::CreateImm(0));