SDTCisVT<1, i32>, SDTCisVT<2, OtherVT>
]>;
+def SDT_PPClbrx : SDTypeProfile<1, 3, [
+ SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
+]>;
+def SDT_PPCstbrx : SDTypeProfile<0, 4, [
+ SDTCisVT<0, i32>, SDTCisPtrTy<1>, SDTCisVT<2, OtherVT>, SDTCisVT<3, OtherVT>
+]>;
+
//===----------------------------------------------------------------------===//
// PowerPC specific DAG Nodes.
//
def PPCstd_32 : SDNode<"PPCISD::STD_32" , SDTStore, [SDNPHasChain]>;
// These are target-independent nodes, but have target-specific formats.
-def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,[SDNPHasChain]>;
-def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,[SDNPHasChain]>;
+def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_PPCCallSeq,
+ [SDNPHasChain, SDNPOutFlag]>;
+def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_PPCCallSeq,
+ [SDNPHasChain, SDNPOutFlag]>;
-def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisVT<0, i32>]>;
+def SDT_PPCCall : SDTypeProfile<0, -1, [SDTCisInt<0>]>;
def PPCcall : SDNode<"PPCISD::CALL", SDT_PPCCall,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def PPCmtctr : SDNode<"PPCISD::MTCTR", SDT_PPCCall,
def PPCcondbranch : SDNode<"PPCISD::COND_BRANCH", SDT_PPCcondbr,
[SDNPHasChain, SDNPOptInFlag]>;
+def PPClbrx : SDNode<"PPCISD::LBRX", SDT_PPClbrx, [SDNPHasChain]>;
+def PPCstbrx : SDNode<"PPCISD::STBRX", SDT_PPCstbrx, [SDNPHasChain]>;
+
//===----------------------------------------------------------------------===//
// PowerPC specific transformation functions and pattern fragments.
//
return getI32Imm(31 - N->getValue());
}]>;
-def SHL64 : SDNodeXForm<imm, [{
- // Transformation function: 63 - imm
- return getI32Imm(63 - N->getValue());
-}]>;
-
def SRL32 : SDNodeXForm<imm, [{
// Transformation function: 32 - imm
return N->getValue() ? getI32Imm(32 - N->getValue()) : getI32Imm(0);
}]>;
-def SRL64 : SDNodeXForm<imm, [{
- // Transformation function: 64 - imm
- return N->getValue() ? getI32Imm(64 - N->getValue()) : getI32Imm(0);
-}]>;
-
def LO16 : SDNodeXForm<imm, [{
// Transformation function: get the low 16 bits.
return getI32Imm((unsigned short)N->getValue());
signed int Val = N->getValue();
return getI32Imm((Val - (signed short)Val) >> 16);
}]>;
+def MB : SDNodeXForm<imm, [{
+ // Transformation function: get the start bit of a mask
+ unsigned mb, me;
+ (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
+ return getI32Imm(mb);
+}]>;
+def ME : SDNodeXForm<imm, [{
+ // Transformation function: get the end bit of a mask
+ unsigned mb, me;
+ (void)isRunOfOnes((unsigned)N->getValue(), mb, me);
+ return getI32Imm(me);
+}]>;
+def maskimm32 : PatLeaf<(imm), [{
+ // maskImm predicate - True if immediate is a run of ones.
+ unsigned mb, me;
+ if (N->getValueType(0) == MVT::i32)
+ return isRunOfOnes((unsigned)N->getValue(), mb, me);
+ else
+ return false;
+}]>;
def immSExt16 : PatLeaf<(imm), [{
// immSExt16 predicate - True if the immediate fits in a 16-bit sign extended
// field. Used by instructions like 'addi'.
- return (int)N->getValue() == (short)N->getValue();
+ if (N->getValueType(0) == MVT::i32)
+ return (int32_t)N->getValue() == (short)N->getValue();
+ else
+ return (int64_t)N->getValue() == (short)N->getValue();
}]>;
def immZExt16 : PatLeaf<(imm), [{
// immZExt16 predicate - True if the immediate fits in a 16-bit zero extended
// field. Used by instructions like 'ori'.
- return (unsigned)N->getValue() == (unsigned short)N->getValue();
+ return (uint64_t)N->getValue() == (unsigned short)N->getValue();
}], LO16>;
-def imm16Shifted : PatLeaf<(imm), [{
- // imm16Shifted predicate - True if only bits in the top 16-bits of the
- // immediate are set. Used by instructions like 'addis'.
+// imm16Shifted* - These match immediates where the low 16-bits are zero. There
+// are two forms: imm16ShiftedSExt and imm16ShiftedZExt. These two forms are
+// identical in 32-bit mode, but in 64-bit mode, they return true if the
+// immediate fits into a sign/zero extended 32-bit immediate (with the low bits
+// clear).
+def imm16ShiftedZExt : PatLeaf<(imm), [{
+ // imm16ShiftedZExt predicate - True if only bits in the top 16-bits of the
+ // immediate are set. Used by instructions like 'xoris'.
+ return (N->getValue() & ~uint64_t(0xFFFF0000)) == 0;
+}], HI16>;
+
+def imm16ShiftedSExt : PatLeaf<(imm), [{
+ // imm16ShiftedSExt predicate - True if only bits in the top 16-bits of the
+ // immediate are set. Used by instructions like 'addis'. Identical to
+ // imm16ShiftedZExt in 32-bit mode.
if (N->getValue() & 0xFFFF) return false;
if (N->getValueType(0) == MVT::i32)
return true;
// PowerPC Flag Definitions.
class isPPC64 { bit PPC64 = 1; }
-class isVMX { bit VMX = 1; }
class isDOT {
list<Register> Defs = [CR0];
bit RC = 1;
// Address operands
def memri : Operand<iPTR> {
let PrintMethod = "printMemRegImm";
- let NumMIOperands = 2;
let MIOperandInfo = (ops i32imm, ptr_rc);
}
def memrr : Operand<iPTR> {
let PrintMethod = "printMemRegReg";
- let NumMIOperands = 2;
let MIOperandInfo = (ops ptr_rc, ptr_rc);
}
def memrix : Operand<iPTR> { // memri where the imm is shifted 2 bits.
let PrintMethod = "printMemRegImmShifted";
- let NumMIOperands = 2;
let MIOperandInfo = (ops i32imm, ptr_rc);
}
// Define PowerPC specific addressing mode.
-def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", []>;
-def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", []>;
-def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[]>;
-def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", []>; // "std"
+def iaddr : ComplexPattern<iPTR, 2, "SelectAddrImm", [], []>;
+def xaddr : ComplexPattern<iPTR, 2, "SelectAddrIdx", [], []>;
+def xoaddr : ComplexPattern<iPTR, 2, "SelectAddrIdxOnly",[], []>;
+def ixaddr : ComplexPattern<iPTR, 2, "SelectAddrImmShift", [], []>; // "std"
//===----------------------------------------------------------------------===//
// PowerPC Instruction Predicate Definitions.
let hasCtrlDep = 1 in {
def ADJCALLSTACKDOWN : Pseudo<(ops u16imm:$amt),
- "; ADJCALLSTACKDOWN",
- [(callseq_start imm:$amt)]>;
+ "${:comment} ADJCALLSTACKDOWN",
+ [(callseq_start imm:$amt)]>, Imp<[R1],[R1]>;
def ADJCALLSTACKUP : Pseudo<(ops u16imm:$amt),
- "; ADJCALLSTACKUP",
- [(callseq_end imm:$amt)]>;
+ "${:comment} ADJCALLSTACKUP",
+ [(callseq_end imm:$amt)]>, Imp<[R1],[R1]>;
def UPDATE_VRSAVE : Pseudo<(ops GPRC:$rD, GPRC:$rS),
"UPDATE_VRSAVE $rD, $rS", []>;
}
-def IMPLICIT_DEF_GPR : Pseudo<(ops GPRC:$rD), "; $rD = IMPLICIT_DEF_GPRC",
+def IMPLICIT_DEF_GPRC: Pseudo<(ops GPRC:$rD),"${:comment}IMPLICIT_DEF_GPRC $rD",
[(set GPRC:$rD, (undef))]>;
-def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "; $rD = IMPLICIT_DEF_F8",
+def IMPLICIT_DEF_F8 : Pseudo<(ops F8RC:$rD), "${:comment} IMPLICIT_DEF_F8 $rD",
[(set F8RC:$rD, (undef))]>;
-def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "; $rD = IMPLICIT_DEF_F4",
+def IMPLICIT_DEF_F4 : Pseudo<(ops F4RC:$rD), "${:comment} IMPLICIT_DEF_F4 $rD",
[(set F4RC:$rD, (undef))]>;
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
// scheduler into a branch sequence.
let usesCustomDAGSchedInserter = 1, // Expanded by the scheduler.
PPC970_Single = 1 in {
- def SELECT_CC_Int : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
- i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
+ def SELECT_CC_I4 : Pseudo<(ops GPRC:$dst, CRRC:$cond, GPRC:$T, GPRC:$F,
+ i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
+ []>;
+ def SELECT_CC_I8 : Pseudo<(ops G8RC:$dst, CRRC:$cond, G8RC:$T, G8RC:$F,
+ i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
+ []>;
def SELECT_CC_F4 : Pseudo<(ops F4RC:$dst, CRRC:$cond, F4RC:$T, F4RC:$F,
- i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
+ i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
+ []>;
def SELECT_CC_F8 : Pseudo<(ops F8RC:$dst, CRRC:$cond, F8RC:$T, F8RC:$F,
- i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
+ i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
+ []>;
def SELECT_CC_VRRC: Pseudo<(ops VRRC:$dst, CRRC:$cond, VRRC:$T, VRRC:$F,
- i32imm:$BROPC), "; SELECT_CC PSEUDO!", []>;
+ i32imm:$BROPC), "${:comment} SELECT_CC PSEUDO!",
+ []>;
}
-let isTerminator = 1, noResults = 1, PPC970_Unit = 7 in {
+let isTerminator = 1, isBarrier = 1, noResults = 1, PPC970_Unit = 7 in {
let isReturn = 1 in
def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB, [(retflag)]>;
def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB, []>;
let isBranch = 1, isTerminator = 1, hasCtrlDep = 1,
noResults = 1, PPC970_Unit = 7 in {
+ // COND_BRANCH is formed before branch selection, it is turned into Bcc below.
def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$dst),
- "; COND_BRANCH $crS, $opc, $dst",
+ "${:comment} COND_BRANCH $crS, $opc, $dst",
[(PPCcondbranch CRRC:$crS, imm:$opc, bb:$dst)]>;
+ let isBarrier = 1 in {
def B : IForm<18, 0, 0, (ops target:$dst),
"b $dst", BrB,
[(br bb:$dst)]>;
+ }
def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block),
"blt $crS, $block", BrB>;
def BL : IForm<18, 0, 1, (ops calltarget:$func, variable_ops),
"bl $func", BrB, []>; // See Pat patterns below.
def BLA : IForm<18, 1, 1, (ops aaddr:$func, variable_ops),
- "bla $func", BrB, [(PPCcall imm:$func)]>;
+ "bla $func", BrB, [(PPCcall (i32 imm:$func))]>;
def BCTRL : XLForm_2_ext<19, 528, 20, 0, 1, (ops variable_ops), "bctrl", BrB,
[(PPCbctrl)]>;
}
// DCB* instructions.
-def DCBZ : DCB_Form<1014, 0, (ops memrr:$dst),
- "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
- PPC970_DGroup_Single;
-def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst),
- "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
- PPC970_DGroup_Single;
+def DCBA : DCB_Form<758, 0, (ops memrr:$dst),
+ "dcba $dst", LdStDCBF, [(int_ppc_dcba xoaddr:$dst)]>,
+ PPC970_DGroup_Single;
+def DCBF : DCB_Form<86, 0, (ops memrr:$dst),
+ "dcbf $dst", LdStDCBF, [(int_ppc_dcbf xoaddr:$dst)]>,
+ PPC970_DGroup_Single;
+def DCBI : DCB_Form<470, 0, (ops memrr:$dst),
+ "dcbi $dst", LdStDCBF, [(int_ppc_dcbi xoaddr:$dst)]>,
+ PPC970_DGroup_Single;
+def DCBST : DCB_Form<54, 0, (ops memrr:$dst),
+ "dcbst $dst", LdStDCBF, [(int_ppc_dcbst xoaddr:$dst)]>,
+ PPC970_DGroup_Single;
+def DCBT : DCB_Form<278, 0, (ops memrr:$dst),
+ "dcbt $dst", LdStDCBF, [(int_ppc_dcbt xoaddr:$dst)]>,
+ PPC970_DGroup_Single;
+def DCBTST : DCB_Form<246, 0, (ops memrr:$dst),
+ "dcbtst $dst", LdStDCBF, [(int_ppc_dcbtst xoaddr:$dst)]>,
+ PPC970_DGroup_Single;
+def DCBZ : DCB_Form<1014, 0, (ops memrr:$dst),
+ "dcbz $dst", LdStDCBF, [(int_ppc_dcbz xoaddr:$dst)]>,
+ PPC970_DGroup_Single;
+def DCBZL : DCB_Form<1014, 1, (ops memrr:$dst),
+ "dcbzl $dst", LdStDCBF, [(int_ppc_dcbzl xoaddr:$dst)]>,
+ PPC970_DGroup_Single;
// D-Form instructions. Most instructions that perform an operation on a
// register and an immediate are of this type.
let isLoad = 1, PPC970_Unit = 2 in {
def LBZ : DForm_1<34, (ops GPRC:$rD, memri:$src),
"lbz $rD, $src", LdStGeneral,
- [(set GPRC:$rD, (zextload iaddr:$src, i8))]>;
+ [(set GPRC:$rD, (zextloadi8 iaddr:$src))]>;
def LHA : DForm_1<42, (ops GPRC:$rD, memri:$src),
"lha $rD, $src", LdStLHA,
- [(set GPRC:$rD, (sextload iaddr:$src, i16))]>,
+ [(set GPRC:$rD, (sextloadi16 iaddr:$src))]>,
PPC970_DGroup_Cracked;
def LHZ : DForm_1<40, (ops GPRC:$rD, memri:$src),
"lhz $rD, $src", LdStGeneral,
- [(set GPRC:$rD, (zextload iaddr:$src, i16))]>;
+ [(set GPRC:$rD, (zextloadi16 iaddr:$src))]>;
def LWZ : DForm_1<32, (ops GPRC:$rD, memri:$src),
"lwz $rD, $src", LdStGeneral,
[(set GPRC:$rD, (load iaddr:$src))]>;
[]>;
def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm),
"addis $rD, $rA, $imm", IntGeneral,
- [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>;
+ [(set GPRC:$rD, (add GPRC:$rA, imm16ShiftedSExt:$imm))]>;
def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym),
"la $rD, $sym($rA)", IntGeneral,
[(set GPRC:$rD, (add GPRC:$rA,
[(set GPRC:$rD, immSExt16:$imm)]>;
def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm),
"lis $rD, $imm", IntGeneral,
- [(set GPRC:$rD, imm16Shifted:$imm)]>;
+ [(set GPRC:$rD, imm16ShiftedSExt:$imm)]>;
}
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
def STB : DForm_3<38, (ops GPRC:$rS, memri:$src),
"stb $rS, $src", LdStGeneral,
- [(truncstore GPRC:$rS, iaddr:$src, i8)]>;
+ [(truncstorei8 GPRC:$rS, iaddr:$src)]>;
def STH : DForm_3<44, (ops GPRC:$rS, memri:$src),
"sth $rS, $src", LdStGeneral,
- [(truncstore GPRC:$rS, iaddr:$src, i16)]>;
+ [(truncstorei16 GPRC:$rS, iaddr:$src)]>;
def STW : DForm_3<36, (ops GPRC:$rS, memri:$src),
"stw $rS, $src", LdStGeneral,
[(store GPRC:$rS, iaddr:$src)]>;
isDOT;
def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
"andis. $dst, $src1, $src2", IntGeneral,
- [(set GPRC:$dst, (and GPRC:$src1, imm16Shifted:$src2))]>,
+ [(set GPRC:$dst, (and GPRC:$src1,imm16ShiftedZExt:$src2))]>,
isDOT;
def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
"ori $dst, $src1, $src2", IntGeneral,
[(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>;
def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
"oris $dst, $src1, $src2", IntGeneral,
- [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>;
+ [(set GPRC:$dst, (or GPRC:$src1, imm16ShiftedZExt:$src2))]>;
def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
"xori $dst, $src1, $src2", IntGeneral,
[(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>;
def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2),
"xoris $dst, $src1, $src2", IntGeneral,
- [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>;
+ [(set GPRC:$dst, (xor GPRC:$src1,imm16ShiftedZExt:$src2))]>;
def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral,
[]>;
-def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm),
- "cmpi $crD, $L, $rA, $imm", IntCompare>;
def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm),
"cmpwi $crD, $rA, $imm", IntCompare>;
-def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2),
- "cmpli $dst, $size, $src1, $src2", IntCompare>;
def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2),
"cmplwi $dst, $src1, $src2", IntCompare>;
}
let isLoad = 1, PPC970_Unit = 2 in {
def LBZX : XForm_1<31, 87, (ops GPRC:$rD, memrr:$src),
"lbzx $rD, $src", LdStGeneral,
- [(set GPRC:$rD, (zextload xaddr:$src, i8))]>;
+ [(set GPRC:$rD, (zextloadi8 xaddr:$src))]>;
def LHAX : XForm_1<31, 343, (ops GPRC:$rD, memrr:$src),
"lhax $rD, $src", LdStLHA,
- [(set GPRC:$rD, (sextload xaddr:$src, i16))]>,
+ [(set GPRC:$rD, (sextloadi16 xaddr:$src))]>,
PPC970_DGroup_Cracked;
def LHZX : XForm_1<31, 279, (ops GPRC:$rD, memrr:$src),
"lhzx $rD, $src", LdStGeneral,
- [(set GPRC:$rD, (zextload xaddr:$src, i16))]>;
+ [(set GPRC:$rD, (zextloadi16 xaddr:$src))]>;
def LWZX : XForm_1<31, 23, (ops GPRC:$rD, memrr:$src),
"lwzx $rD, $src", LdStGeneral,
[(set GPRC:$rD, (load xaddr:$src))]>;
+
+
+def LHBRX : XForm_1<31, 790, (ops GPRC:$rD, memrr:$src),
+ "lhbrx $rD, $src", LdStGeneral,
+ [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i16))]>;
+def LWBRX : XForm_1<31, 534, (ops GPRC:$rD, memrr:$src),
+ "lwbrx $rD, $src", LdStGeneral,
+ [(set GPRC:$rD, (PPClbrx xoaddr:$src, srcvalue:$sv, i32))]>;
+
}
let PPC970_Unit = 1 in { // FXU Operations.
def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"and $rA, $rS, $rB", IntGeneral,
[(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>;
-def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "and. $rA, $rS, $rB", IntGeneral,
- []>, isDOT;
def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"andc $rA, $rS, $rB", IntGeneral,
[(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>;
-def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
+def OR : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"or $rA, $rS, $rB", IntGeneral,
[(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>;
def NOR : XForm_6<31, 124, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"nor $rA, $rS, $rB", IntGeneral,
[(set GPRC:$rA, (not (or GPRC:$rS, GPRC:$rB)))]>;
-def ORo : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
- "or. $rA, $rS, $rB", IntGeneral,
- []>, isDOT;
def ORC : XForm_6<31, 412, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB),
"orc $rA, $rS, $rB", IntGeneral,
[(set GPRC:$rA, (or GPRC:$rS, (not GPRC:$rB)))]>;
let isStore = 1, noResults = 1, PPC970_Unit = 2 in {
def STBX : XForm_8<31, 215, (ops GPRC:$rS, memrr:$dst),
"stbx $rS, $dst", LdStGeneral,
- [(truncstore GPRC:$rS, xaddr:$dst, i8)]>,
+ [(truncstorei8 GPRC:$rS, xaddr:$dst)]>,
PPC970_DGroup_Cracked;
def STHX : XForm_8<31, 407, (ops GPRC:$rS, memrr:$dst),
"sthx $rS, $dst", LdStGeneral,
- [(truncstore GPRC:$rS, xaddr:$dst, i16)]>,
+ [(truncstorei16 GPRC:$rS, xaddr:$dst)]>,
PPC970_DGroup_Cracked;
def STWX : XForm_8<31, 151, (ops GPRC:$rS, memrr:$dst),
"stwx $rS, $dst", LdStGeneral,
def STWUX : XForm_8<31, 183, (ops GPRC:$rS, GPRC:$rA, GPRC:$rB),
"stwux $rS, $rA, $rB", LdStGeneral,
[]>;
+def STHBRX: XForm_8<31, 918, (ops GPRC:$rS, memrr:$dst),
+ "sthbrx $rS, $dst", LdStGeneral,
+ [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i16)]>,
+ PPC970_DGroup_Cracked;
+def STWBRX: XForm_8<31, 662, (ops GPRC:$rS, memrr:$dst),
+ "stwbrx $rS, $dst", LdStGeneral,
+ [(PPCstbrx GPRC:$rS, xoaddr:$dst, srcvalue:$dummy, i32)]>,
+ PPC970_DGroup_Cracked;
}
let PPC970_Unit = 1 in { // FXU Operations.
def SRAWI : XForm_10<31, 824, (ops GPRC:$rA, GPRC:$rS, u5imm:$SH),
"extsh $rA, $rS", IntGeneral,
[(set GPRC:$rA, (sext_inreg GPRC:$rS, i16))]>;
-def CMP : XForm_16<31, 0, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
- "cmp $crD, $long, $rA, $rB", IntCompare>;
-def CMPL : XForm_16<31, 32, (ops CRRC:$crD, i1imm:$long, GPRC:$rA, GPRC:$rB),
- "cmpl $crD, $long, $rA, $rB", IntCompare>;
def CMPW : XForm_16_ext<31, 0, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
"cmpw $crD, $rA, $rB", IntCompare>;
def CMPLW : XForm_16_ext<31, 32, (ops CRRC:$crD, GPRC:$rA, GPRC:$rB),
//
def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file),
- "; .loc $file, $line, $col",
+ "${:comment} .loc $file, $line, $col",
[(dwarf_loc (i32 imm:$line), (i32 imm:$col),
(i32 imm:$file))]>;
def DWARF_LABEL : Pseudo<(ops i32imm:$id),
- "\nLdebug_loc$id:",
+ "\n${:private}debug_loc$id:",
[(dwarf_label (i32 imm:$id))]>;
//===----------------------------------------------------------------------===//
def : Pat<(rotl GPRC:$in, (i32 imm:$imm)),
(RLWINM GPRC:$in, imm:$imm, 0, 31)>;
+// RLWNM
+def : Pat<(and (rotl GPRC:$in, GPRC:$sh), maskimm32:$imm),
+ (RLWNM GPRC:$in, GPRC:$sh, (MB maskimm32:$imm), (ME maskimm32:$imm))>;
+
// Calls
def : Pat<(PPCcall tglobaladdr:$dst),
(BL tglobaladdr:$dst)>;
def : Pat<(shl GPRC:$rS, GPRC:$rB),
(SLW GPRC:$rS, GPRC:$rB)>;
-def : Pat<(zextload iaddr:$src, i1),
+def : Pat<(zextloadi1 iaddr:$src),
(LBZ iaddr:$src)>;
-def : Pat<(zextload xaddr:$src, i1),
+def : Pat<(zextloadi1 xaddr:$src),
(LBZX xaddr:$src)>;
-def : Pat<(extload iaddr:$src, i1),
+def : Pat<(extloadi1 iaddr:$src),
(LBZ iaddr:$src)>;
-def : Pat<(extload xaddr:$src, i1),
+def : Pat<(extloadi1 xaddr:$src),
(LBZX xaddr:$src)>;
-def : Pat<(extload iaddr:$src, i8),
+def : Pat<(extloadi8 iaddr:$src),
(LBZ iaddr:$src)>;
-def : Pat<(extload xaddr:$src, i8),
+def : Pat<(extloadi8 xaddr:$src),
(LBZX xaddr:$src)>;
-def : Pat<(extload iaddr:$src, i16),
+def : Pat<(extloadi16 iaddr:$src),
(LHZ iaddr:$src)>;
-def : Pat<(extload xaddr:$src, i16),
+def : Pat<(extloadi16 xaddr:$src),
(LHZX xaddr:$src)>;
-def : Pat<(extload iaddr:$src, f32),
+def : Pat<(extloadf32 iaddr:$src),
(FMRSD (LFS iaddr:$src))>;
-def : Pat<(extload xaddr:$src, f32),
+def : Pat<(extloadf32 xaddr:$src),
(FMRSD (LFSX xaddr:$src))>;
include "PPCInstrAltivec.td"