Ok for vector_shuffle mask to contain undef elements.

[oota-llvm.git] / lib / Target / PowerPC / PPCRegisterInfo.cpp

diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 148449c6d4d1d6a38e795435f74dca85e02ff330..679b233bc684907ed8a1122a7a7726f9c4999679 100644 (file)
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -21,6 +21,7 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
+#include "llvm/CodeGen/MachineLocation.h"
 #include "llvm/Target/TargetFrameInfo.h"
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/TargetOptions.h"
@@ -50,6 +51,9 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
                                      unsigned SrcReg, int FrameIdx,
                                      const TargetRegisterClass *RC) const {
   if (SrcReg == PPC::LR) {
+    // FIXME: this spills LR immediately to memory in one step.  To do this, we
+    // use R11, which we know cannot be used in the prolog/epilog.  This is a
+    // hack.
     BuildMI(MBB, MI, PPC::MFLR, 1, PPC::R11);
     addFrameReference(BuildMI(MBB, MI, PPC::STW, 3).addReg(PPC::R11), FrameIdx);
   } else if (RC == PPC::CRRCRegisterClass) {
@@ -63,6 +67,15 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
     addFrameReference(BuildMI(MBB, MI, PPC::STFD, 3).addReg(SrcReg),FrameIdx);
   } else if (RC == PPC::F4RCRegisterClass) {
     addFrameReference(BuildMI(MBB, MI, PPC::STFS, 3).addReg(SrcReg),FrameIdx);
+  } else if (RC == PPC::VRRCRegisterClass) {
+    // We don't have indexed addressing for vector loads.  Emit:
+    // R11 = ADDI FI#
+    // Dest = LVX R0, R11
+    // 
+    // FIXME: We use R0 here, because it isn't available for RA.
+    addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
+    BuildMI(MBB, MI, PPC::STVX, 3)
+      .addReg(SrcReg).addReg(PPC::R0).addReg(PPC::R0);
   } else {
     assert(0 && "Unknown regclass!");
     abort();
@@ -88,6 +101,14 @@ PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
     addFrameReference(BuildMI(MBB, MI, PPC::LFD, 2, DestReg), FrameIdx);
   } else if (RC == PPC::F4RCRegisterClass) {
     addFrameReference(BuildMI(MBB, MI, PPC::LFS, 2, DestReg), FrameIdx);
+  } else if (RC == PPC::VRRCRegisterClass) {
+    // We don't have indexed addressing for vector loads.  Emit:
+    // R11 = ADDI FI#
+    // Dest = LVX R0, R11
+    // 
+    // FIXME: We use R0 here, because it isn't available for RA.
+    addFrameReference(BuildMI(MBB, MI, PPC::ADDI, 1, PPC::R0), FrameIdx, 0, 0);
+    BuildMI(MBB, MI, PPC::LVX, 2, DestReg).addReg(PPC::R0).addReg(PPC::R0);
   } else {
     assert(0 && "Unknown regclass!");
     abort();
@@ -98,8 +119,6 @@ void PPCRegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
                                    MachineBasicBlock::iterator MI,
                                    unsigned DestReg, unsigned SrcReg,
                                    const TargetRegisterClass *RC) const {
-  MachineInstr *I;
-
   if (RC == PPC::GPRCRegisterClass) {
     BuildMI(MBB, MI, PPC::OR4, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
   } else if (RC == PPC::G8RCRegisterClass) {
@@ -258,7 +277,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
     case PPC::LWA:
     case PPC::LD:
     case PPC::STD:
-    case PPC::STDU:
+    case PPC::STD_32:
       assert((Offset & 3) == 0 && "Invalid frame offset!");
       Offset >>= 2;    // The actual encoded value has the low two bits zero.
       break;
@@ -428,5 +447,9 @@ void PPCRegisterInfo::emitEpilogue(MachineFunction &MF,
   }
 }
 
+unsigned PPCRegisterInfo::getFrameRegister(MachineFunction &MF) const {
+  return getDwarfRegNum(hasFP(MF) ? PPC::R31 : PPC::R1);
+}
+
 #include "PPCGenRegisterInfo.inc"