//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
-// This file contains the PowerPC implementation of the MRegisterInfo class.
+// This file contains the PowerPC implementation of the TargetRegisterInfo
+// class.
//
//===----------------------------------------------------------------------===//
#define POWERPC32_REGISTERINFO_H
#include "PPC.h"
-#include "PPCGenRegisterInfo.h.inc"
#include <map>
-namespace llvm {
+#define GET_REGINFO_HEADER
+#include "PPCGenRegisterInfo.inc"
+namespace llvm {
+class PPCSubtarget;
+class TargetInstrInfo;
class Type;
class PPCRegisterInfo : public PPCGenRegisterInfo {
std::map<unsigned, unsigned> ImmToIdxMap;
+ const PPCSubtarget &Subtarget;
+ const TargetInstrInfo &TII;
public:
- PPCRegisterInfo();
+ PPCRegisterInfo(const PPCSubtarget &SubTarget, const TargetInstrInfo &tii);
+
+ /// getPointerRegClass - Return the register class to use to hold pointers.
+ /// This is used for addressing modes.
+ virtual const TargetRegisterClass *getPointerRegClass(unsigned Kind=0) const;
+
+ unsigned getRegPressureLimit(const TargetRegisterClass *RC,
+ MachineFunction &MF) const;
/// Code Generation virtual methods...
- void storeRegToStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- unsigned SrcReg, int FrameIndex,
- const TargetRegisterClass *RC) const;
+ const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
- void loadRegFromStackSlot(MachineBasicBlock &MBB,
- MachineBasicBlock::iterator MBBI,
- unsigned DestReg, int FrameIndex,
- const TargetRegisterClass *RC) const;
+ BitVector getReservedRegs(const MachineFunction &MF) const;
- void copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
- unsigned DestReg, unsigned SrcReg,
- const TargetRegisterClass *RC) const;
+ /// requiresRegisterScavenging - We require a register scavenger.
+ /// FIXME (64-bit): Should be inlined.
+ bool requiresRegisterScavenging(const MachineFunction &MF) const;
- unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
-
- /// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
- /// copy instructions, turning them into load/store instructions.
- virtual MachineInstr* foldMemoryOperand(MachineInstr* MI, unsigned OpNum,
- int FrameIndex) const;
-
void eliminateCallFramePseudoInstr(MachineFunction &MF,
MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const;
- void eliminateFrameIndex(MachineBasicBlock::iterator II) const;
+ void lowerDynamicAlloc(MachineBasicBlock::iterator II,
+ int SPAdj, RegScavenger *RS) const;
+ void lowerCRSpilling(MachineBasicBlock::iterator II, unsigned FrameIndex,
+ int SPAdj, RegScavenger *RS) const;
+ void eliminateFrameIndex(MachineBasicBlock::iterator II,
+ int SPAdj, RegScavenger *RS = NULL) const;
+
+ // Debug information queries.
+ unsigned getFrameRegister(const MachineFunction &MF) const;
- void emitPrologue(MachineFunction &MF) const;
- void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
+ // Exception handling queries.
+ unsigned getEHExceptionRegister() const;
+ unsigned getEHHandlerRegister() const;
};
} // end namespace llvm