Const-qualify getPreIndexedAddressParts and friends.

[oota-llvm.git] / lib / Target / PowerPC / PPCRegisterInfo.td

diff --git a/lib/Target/PowerPC/PPCRegisterInfo.td b/lib/Target/PowerPC/PPCRegisterInfo.td
index 245d7e15055d81baac362592d6f1f4ce32575efb..9e15a55781c88732a592c07c9548b63738890410 100644 (file)
--- a/lib/Target/PowerPC/PPCRegisterInfo.td
+++ b/lib/Target/PowerPC/PPCRegisterInfo.td
@@ -1,4 +1,4 @@
-//===- PowerPCRegisterInfo.td - The PowerPC Register File --*- tablegen -*-===//
+//===- PPCRegisterInfo.td - The PowerPC Register File ------*- tablegen -*-===//
 // 
 //                     The LLVM Compiler Infrastructure
 //
@@ -22,7 +22,7 @@ class GPR<bits<5> num, string n> : PPCReg<n> {
 }
 
 // GP8 - One of the 32 64-bit general-purpose registers
-class GP8<GPR SubReg> : PPCReg<SubReg.Name> {
+class GP8<GPR SubReg, string n> : PPCReg<n> {
   field bits<5> Num = SubReg.Num;
   let SubRegs = [SubReg];
 }
@@ -88,38 +88,38 @@ def R30 : GPR<30, "r30">, DwarfRegNum<[30]>;
 def R31 : GPR<31, "r31">, DwarfRegNum<[31]>;
 
 // 64-bit General-purpose registers
-def X0  : GP8< R0>, DwarfRegNum<[0]>;
-def X1  : GP8< R1>, DwarfRegNum<[1]>;
-def X2  : GP8< R2>, DwarfRegNum<[2]>;
-def X3  : GP8< R3>, DwarfRegNum<[3]>;
-def X4  : GP8< R4>, DwarfRegNum<[4]>;
-def X5  : GP8< R5>, DwarfRegNum<[5]>;
-def X6  : GP8< R6>, DwarfRegNum<[6]>;
-def X7  : GP8< R7>, DwarfRegNum<[7]>;
-def X8  : GP8< R8>, DwarfRegNum<[8]>;
-def X9  : GP8< R9>, DwarfRegNum<[9]>;
-def X10 : GP8<R10>, DwarfRegNum<[10]>;
-def X11 : GP8<R11>, DwarfRegNum<[11]>;
-def X12 : GP8<R12>, DwarfRegNum<[12]>;
-def X13 : GP8<R13>, DwarfRegNum<[13]>;
-def X14 : GP8<R14>, DwarfRegNum<[14]>;
-def X15 : GP8<R15>, DwarfRegNum<[15]>;
-def X16 : GP8<R16>, DwarfRegNum<[16]>;
-def X17 : GP8<R17>, DwarfRegNum<[17]>;
-def X18 : GP8<R18>, DwarfRegNum<[18]>;
-def X19 : GP8<R19>, DwarfRegNum<[19]>;
-def X20 : GP8<R20>, DwarfRegNum<[20]>;
-def X21 : GP8<R21>, DwarfRegNum<[21]>;
-def X22 : GP8<R22>, DwarfRegNum<[22]>;
-def X23 : GP8<R23>, DwarfRegNum<[23]>;
-def X24 : GP8<R24>, DwarfRegNum<[24]>;
-def X25 : GP8<R25>, DwarfRegNum<[25]>;
-def X26 : GP8<R26>, DwarfRegNum<[26]>;
-def X27 : GP8<R27>, DwarfRegNum<[27]>;
-def X28 : GP8<R28>, DwarfRegNum<[28]>;
-def X29 : GP8<R29>, DwarfRegNum<[29]>;
-def X30 : GP8<R30>, DwarfRegNum<[30]>;
-def X31 : GP8<R31>, DwarfRegNum<[31]>;
+def X0  : GP8< R0,  "r0">, DwarfRegNum<[0]>;
+def X1  : GP8< R1,  "r1">, DwarfRegNum<[1]>;
+def X2  : GP8< R2,  "r2">, DwarfRegNum<[2]>;
+def X3  : GP8< R3,  "r3">, DwarfRegNum<[3]>;
+def X4  : GP8< R4,  "r4">, DwarfRegNum<[4]>;
+def X5  : GP8< R5,  "r5">, DwarfRegNum<[5]>;
+def X6  : GP8< R6,  "r6">, DwarfRegNum<[6]>;
+def X7  : GP8< R7,  "r7">, DwarfRegNum<[7]>;
+def X8  : GP8< R8,  "r8">, DwarfRegNum<[8]>;
+def X9  : GP8< R9,  "r9">, DwarfRegNum<[9]>;
+def X10 : GP8<R10, "r10">, DwarfRegNum<[10]>;
+def X11 : GP8<R11, "r11">, DwarfRegNum<[11]>;
+def X12 : GP8<R12, "r12">, DwarfRegNum<[12]>;
+def X13 : GP8<R13, "r13">, DwarfRegNum<[13]>;
+def X14 : GP8<R14, "r14">, DwarfRegNum<[14]>;
+def X15 : GP8<R15, "r15">, DwarfRegNum<[15]>;
+def X16 : GP8<R16, "r16">, DwarfRegNum<[16]>;
+def X17 : GP8<R17, "r17">, DwarfRegNum<[17]>;
+def X18 : GP8<R18, "r18">, DwarfRegNum<[18]>;
+def X19 : GP8<R19, "r19">, DwarfRegNum<[19]>;
+def X20 : GP8<R20, "r20">, DwarfRegNum<[20]>;
+def X21 : GP8<R21, "r21">, DwarfRegNum<[21]>;
+def X22 : GP8<R22, "r22">, DwarfRegNum<[22]>;
+def X23 : GP8<R23, "r23">, DwarfRegNum<[23]>;
+def X24 : GP8<R24, "r24">, DwarfRegNum<[24]>;
+def X25 : GP8<R25, "r25">, DwarfRegNum<[25]>;
+def X26 : GP8<R26, "r26">, DwarfRegNum<[26]>;
+def X27 : GP8<R27, "r27">, DwarfRegNum<[27]>;
+def X28 : GP8<R28, "r28">, DwarfRegNum<[28]>;
+def X29 : GP8<R29, "r29">, DwarfRegNum<[29]>;
+def X30 : GP8<R30, "r30">, DwarfRegNum<[30]>;
+def X31 : GP8<R31, "r31">, DwarfRegNum<[31]>;
 
 // Floating-point registers
 def F0  : FPR< 0,  "f0">, DwarfRegNum<[32]>;
@@ -254,6 +254,16 @@ def CTR8 : SPR<9, "ctr">, DwarfRegNum<[66]>;
 // VRsave register
 def VRSAVE: SPR<256, "VRsave">, DwarfRegNum<[107]>;
 
+// FP rounding mode:  bits 30 and 31 of the FP status and control register
+// This is not allocated as a normal register; it appears only in
+// Uses and Defs.  The ABI says it needs to be preserved by a function,
+// but this is not achieved by saving and restoring it as with
+// most registers, it has to be done in code; to make this work all the
+// return and call instructions are described as Uses of RM, so instructions
+// that do nothing but change RM will not get deleted.
+// Also, in the architecture it is not really a SPR; 512 is arbitrary.
+def RM: SPR<512, "**ROUNDING MODE**">, DwarfRegNum<[0]>;
+
 /// Register classes
 // Allocate volatiles first
 // then nonvolatiles in reverse order since stmw/lmw save from rN to r31
@@ -330,4 +340,21 @@ def VRRC : RegisterClass<"PPC", [v16i8,v8i16,v4i32,v4f32], 128,
 
 def CRRC : RegisterClass<"PPC", [i32], 32, [CR0, CR1, CR5, CR6, CR7, CR2, 
   CR3, CR4]>;
-  
+
+def CRBITRC : RegisterClass<"PPC", [i32], 32,
+  [CR0LT, CR0GT, CR0EQ, CR0UN,
+   CR1LT, CR1GT, CR1EQ, CR1UN,
+   CR2LT, CR2GT, CR2EQ, CR2UN,
+   CR3LT, CR3GT, CR3EQ, CR3UN,
+   CR4LT, CR4GT, CR4EQ, CR4UN,
+   CR5LT, CR5GT, CR5EQ, CR5UN,
+   CR6LT, CR6GT, CR6EQ, CR6UN,
+   CR7LT, CR7GT, CR7EQ, CR7UN
+  ]>
+{
+  let CopyCost = -1;
+}
+
+
+def CTRRC : RegisterClass<"PPC", [i32], 32, [CTR]>;
+def CTRRC8 : RegisterClass<"PPC", [i64], 64, [CTR8]>;