-//===- PPCSchedule.td - PowerPC Scheduling Definitions -----*- tablegen -*-===//
-//
+//===-- PPCSchedule.td - PowerPC Scheduling Definitions ----*- tablegen -*-===//
+//
// The LLVM Compiler Infrastructure
//
-// This file was developed by James M. Laskey and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
//===----------------------------------------------------------------------===//
-#include "../Target.td"
-
//===----------------------------------------------------------------------===//
// Functional units across PowerPC chips sets
//
def SRU : FuncUnit; // special register unit
def IU1 : FuncUnit; // integer unit 1 (simple)
def IU2 : FuncUnit; // integer unit 2 (complex)
-def IU3 : FuncUnit; // integer unit 3 (7450 simple)
-def IU4 : FuncUnit; // integer unit 4 (7450 simple)
def FPU1 : FuncUnit; // floating point unit 1
def FPU2 : FuncUnit; // floating point unit 2
def VPU : FuncUnit; // vector permutation unit
def VIU2 : FuncUnit; // vector integer unit 2 (complex)
def VFPU : FuncUnit; // vector floating point unit
-
//===----------------------------------------------------------------------===//
// Instruction Itinerary classes used for PowerPC
//
+def IntSimple : InstrItinClass;
def IntGeneral : InstrItinClass;
def IntCompare : InstrItinClass;
def IntDivD : InstrItinClass;
def IntMulLI : InstrItinClass;
def IntRFID : InstrItinClass;
def IntRotateD : InstrItinClass;
+def IntRotateDI : InstrItinClass;
def IntRotate : InstrItinClass;
def IntShift : InstrItinClass;
def IntTrapD : InstrItinClass;
def LdStDCBA : InstrItinClass;
def LdStDCBF : InstrItinClass;
def LdStDCBI : InstrItinClass;
-def LdStDCBT : InstrItinClass;
+def LdStLoad : InstrItinClass;
+def LdStLoadUpd : InstrItinClass;
+def LdStStore : InstrItinClass;
+def LdStStoreUpd : InstrItinClass;
def LdStDSS : InstrItinClass;
def LdStICBI : InstrItinClass;
-def LdStLBZUX : InstrItinClass;
def LdStLD : InstrItinClass;
+def LdStLDU : InstrItinClass;
def LdStLDARX : InstrItinClass;
def LdStLFD : InstrItinClass;
def LdStLFDU : InstrItinClass;
def LdStLHA : InstrItinClass;
+def LdStLHAU : InstrItinClass;
def LdStLMW : InstrItinClass;
-def LdStLVEBX : InstrItinClass;
+def LdStLVecX : InstrItinClass;
def LdStLWA : InstrItinClass;
def LdStLWARX : InstrItinClass;
def LdStSLBIA : InstrItinClass;
def LdStSLBIE : InstrItinClass;
def LdStSTD : InstrItinClass;
def LdStSTDCX : InstrItinClass;
+def LdStSTDU : InstrItinClass;
+def LdStSTFD : InstrItinClass;
+def LdStSTFDU : InstrItinClass;
def LdStSTVEBX : InstrItinClass;
def LdStSTWCX : InstrItinClass;
def LdStSync : InstrItinClass;
def SprRFI : InstrItinClass;
def SprSC : InstrItinClass;
def FPGeneral : InstrItinClass;
+def FPAddSub : InstrItinClass;
def FPCompare : InstrItinClass;
def FPDivD : InstrItinClass;
def FPDivS : InstrItinClass;
//===----------------------------------------------------------------------===//
// Processor instruction itineraries.
-#include "PPCScheduleG3.td"
-#include "PPCScheduleG4.td"
-#include "PPCScheduleG4Plus.td"
-#include "PPCScheduleG5.td"
+include "PPCScheduleG3.td"
+include "PPCSchedule440.td"
+include "PPCScheduleG4.td"
+include "PPCScheduleG4Plus.td"
+include "PPCScheduleG5.td"
+include "PPCScheduleA2.td"
+include "PPCScheduleE500mc.td"
+include "PPCScheduleE5500.td"
//===----------------------------------------------------------------------===//
// Instruction to itinerary class map - When add new opcodes to the supported
//
// opcode itinerary class
// ====== ===============
-// add IntGeneral
+// add IntSimple
// addc IntGeneral
// adde IntGeneral
-// addi IntGeneral
+// addi IntSimple
// addic IntGeneral
// addic. IntGeneral
-// addis IntGeneral
+// addis IntSimple
// addme IntGeneral
// addze IntGeneral
-// and IntGeneral
-// andc IntGeneral
+// and IntSimple
+// andc IntSimple
// andi. IntGeneral
// andis. IntGeneral
// b BrB
// dcbf LdStDCBF
// dcbi LdStDCBI
// dcbst LdStDCBF
-// dcbt LdStDCBT
-// dcbtst LdStDCBT
+// dcbt LdStLoad
+// dcbtst LdStLoad
// dcbz LdStDCBF
// divd IntDivD
// divdu IntDivD
// dss LdStDSS
// dst LdStDSS
// dstst LdStDSS
-// eciwx LdStDCBT
-// ecowx LdStDCBT
-// eieio LdStDCBT
-// eqv IntGeneral
-// extsb IntGeneral
-// extsh IntGeneral
-// extsw IntRotateD
+// eciwx LdStLoad
+// ecowx LdStLoad
+// eieio LdStLoad
+// eqv IntSimple
+// extsb IntSimple
+// extsh IntSimple
+// extsw IntSimple
// fabs FPGeneral
-// fadd FPGeneral
+// fadd FPAddSub
// fadds FPGeneral
// fcfid FPGeneral
// fcmpo FPCompare
// fsel FPGeneral
// fsqrt FPSqrt
// fsqrts FPSqrt
-// fsub FPGeneral
+// fsub FPAddSub
// fsubs FPGeneral
// icbi LdStICBI
// isync SprISYNC
-// lbz LdStDCBT
-// lbzu LdStDCBT
-// lbzux LdStLBZUX
-// lbzx LdStDCBT
+// lbz LdStLoad
+// lbzu LdStLoadUpd
+// lbzux LdStLoadUpd
+// lbzx LdStLoad
// ld LdStLD
// ldarx LdStLDARX
-// ldu LdStLD
-// ldux LdStLD
+// ldu LdStLDU
+// ldux LdStLDU
// ldx LdStLD
// lfd LdStLFD
// lfdu LdStLFDU
// lfdux LdStLFDU
-// lfdx LdStLFDU
-// lfs LdStLFDU
+// lfdx LdStLFD
+// lfs LdStLFD
// lfsu LdStLFDU
// lfsux LdStLFDU
-// lfsx LdStLFDU
+// lfsx LdStLFD
// lha LdStLHA
-// lhau LdStLHA
-// lhaux LdStLHA
+// lhau LdStLHAU
+// lhaux LdStLHAU
// lhax LdStLHA
-// lhbrx LdStDCBT
-// lhz LdStDCBT
-// lhzu LdStDCBT
-// lhzux LdStLBZUX
-// lhzx LdStDCBT
+// lhbrx LdStLoad
+// lhz LdStLoad
+// lhzu LdStLoadUpd
+// lhzux LdStLoadUpd
+// lhzx LdStLoad
// lmw LdStLMW
// lswi LdStLMW
// lswx LdStLMW
-// lvebx LdStLVEBX
-// lvehx LdStLVEBX
-// lvewx LdStLVEBX
-// lvsl LdStLVEBX
-// lvsr LdStLVEBX
-// lvx LdStLVEBX
-// lvxl LdStLVEBX
+// lvebx LdStLVecX
+// lvehx LdStLVecX
+// lvewx LdStLVecX
+// lvsl LdStLVecX
+// lvsr LdStLVecX
+// lvx LdStLVecX
+// lvxl LdStLVecX
// lwa LdStLWA
// lwarx LdStLWARX
-// lwaux LdStLHA
+// lwaux LdStLHAU
// lwax LdStLHA
-// lwbrx LdStDCBT
-// lwz LdStDCBT
-// lwzu LdStDCBT
-// lwzux LdStLBZUX
-// lwzx LdStDCBT
+// lwbrx LdStLoad
+// lwz LdStLoad
+// lwzu LdStLoadUpd
+// lwzux LdStLoadUpd
+// lwzx LdStLoad
// mcrf BrMCR
// mcrfs FPGeneral
// mcrxr BrMCRX
// mulld IntMulHD
// mulli IntMulLI
// mullw IntMulHW
-// nand IntGeneral
-// neg IntGeneral
-// nor IntGeneral
-// or IntGeneral
-// orc IntGeneral
-// ori IntGeneral
-// oris IntGeneral
+// nand IntSimple
+// neg IntSimple
+// nor IntSimple
+// or IntSimple
+// orc IntSimple
+// ori IntSimple
+// oris IntSimple
// rfi SprRFI
// rfid IntRFID
// rldcl IntRotateD
// rldcr IntRotateD
-// rldic IntRotateD
-// rldicl IntRotateD
-// rldicr IntRotateD
-// rldimi IntRotateD
+// rldic IntRotateDI
+// rldicl IntRotateDI
+// rldicr IntRotateDI
+// rldimi IntRotateDI
// rlwimi IntRotate
// rlwinm IntGeneral
// rlwnm IntGeneral
// sld IntRotateD
// slw IntGeneral
// srad IntRotateD
-// sradi IntRotateD
+// sradi IntRotateDI
// sraw IntShift
// srawi IntShift
// srd IntRotateD
// srw IntGeneral
-// stb LdStDCBT
-// stbu LdStDCBT
-// stbux LdStDCBT
-// stbx LdStDCBT
+// stb LdStStore
+// stbu LdStStoreUpd
+// stbux LdStStoreUpd
+// stbx LdStStore
// std LdStSTD
// stdcx. LdStSTDCX
-// stdu LdStSTD
-// stdux LdStSTD
+// stdu LdStSTDU
+// stdux LdStSTDU
// stdx LdStSTD
-// stfd LdStLBZUX
-// stfdu LdStLBZUX
-// stfdux LdStLBZUX
-// stfdx LdStLBZUX
-// stfiwx LdStLBZUX
-// stfs LdStLBZUX
-// stfsu LdStLBZUX
-// stfsux LdStLBZUX
-// stfsx LdStLBZUX
-// sth LdStDCBT
-// sthbrx LdStDCBT
-// sthu LdStDCBT
-// sthux LdStDCBT
-// sthx LdStDCBT
+// stfd LdStSTFD
+// stfdu LdStSTFDU
+// stfdux LdStSTFDU
+// stfdx LdStSTFD
+// stfiwx LdStSTFD
+// stfs LdStSTFD
+// stfsu LdStSTFDU
+// stfsux LdStSTFDU
+// stfsx LdStSTFD
+// sth LdStStore
+// sthbrx LdStStore
+// sthu LdStStoreUpd
+// sthux LdStStoreUpd
+// sthx LdStStore
// stmw LdStLMW
// stswi LdStLMW
// stswx LdStLMW
// stvewx LdStSTVEBX
// stvx LdStSTVEBX
// stvxl LdStSTVEBX
-// stw LdStDCBT
-// stwbrx LdStDCBT
+// stw LdStStore
+// stwbrx LdStStore
// stwcx. LdStSTWCX
-// stwu LdStDCBT
-// stwux LdStDCBT
-// stwx LdStDCBT
+// stwu LdStStoreUpd
+// stwux LdStStoreUpd
+// stwx LdStStore
// subf IntGeneral
// subfc IntGeneral
// subfe IntGeneral
// vupklsb VecPerm
// vupklsh VecPerm
// vxor VecGeneral
-// xor IntGeneral
-// xori IntGeneral
-// xoris IntGeneral
-//
-
-
-//===----------------------------------------------------------------------===//
-// PowerPC Subtarget features.
-//
-
-def F64Bit : SubtargetFeature<"64bit",
- "Should 64 bit instructions be used">;
-def F64BitRegs : SubtargetFeature<"64bitregs",
- "Should 64 bit registers be used">;
-def FAltivec : SubtargetFeature<"altivec",
- "Should Altivec instructions be used">;
-def FGPUL : SubtargetFeature<"gpul",
- "Should GPUL instructions be used">;
-def FFSQRT : SubtargetFeature<"fsqrt",
- "Should the fsqrt instruction be used">;
-
-//===----------------------------------------------------------------------===//
-// PowerPC chips sets supported
+// xor IntSimple
+// xori IntSimple
+// xoris IntSimple
//
-
-def : Processor<"601", G3Itineraries, []>;
-def : Processor<"602", G3Itineraries, []>;
-def : Processor<"603", G3Itineraries, []>;
-def : Processor<"604", G3Itineraries, []>;
-def : Processor<"750", G3Itineraries, []>;
-def : Processor<"7400", G4Itineraries, [FAltivec]>;
-def : Processor<"g4", G4Itineraries, [FAltivec]>;
-def : Processor<"7450", G4PlusItineraries, [FAltivec]>;
-def : Processor<"g4+", G4PlusItineraries, [FAltivec]>;
-def : Processor<"970", G5Itineraries,
- [FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>;
-def : Processor<"g5", G5Itineraries,
- [FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>;
-
-
projects / oota-llvm.git / blobdiff