[SystemZ] Clean up warning

[oota-llvm.git] / lib / Target / PowerPC / PPCSchedule440.td

diff --git a/lib/Target/PowerPC/PPCSchedule440.td b/lib/Target/PowerPC/PPCSchedule440.td
index 4523cfeb85f9f0267df8095ff9e4b3cf977edd6d..04a43bc03251a45156adc56b89856aa9d79719e8 100644 (file)
--- a/lib/Target/PowerPC/PPCSchedule440.td
+++ b/lib/Target/PowerPC/PPCSchedule440.td
@@ -110,7 +110,7 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
                                  InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
                                  InstrStage<1, [P440_IWB, P440_JWB]>],
-                                [6, 4, 4],
+                                [2, 0, 0],
                                 [P440_GPR_Bypass,
                                  P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_IntGeneral, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
@@ -118,29 +118,37 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
                                  InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
                                  InstrStage<1, [P440_IWB, P440_JWB]>],
-                                [6, 4, 4],
+                                [2, 0, 0],
                                 [P440_GPR_Bypass,
                                  P440_GPR_Bypass, P440_GPR_Bypass]>,
+  InstrItinData<IIC_IntISEL,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
+                                 InstrStage<1, [P440_IRACC, P440_LRACC]>,
+                                 InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
+                                 InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
+                                 InstrStage<1, [P440_IWB, P440_JWB]>],
+                                [2, 0, 0, 0],
+                                [P440_GPR_Bypass,
+                                 P440_GPR_Bypass, P440_GPR_Bypass, NoBypass]>,
   InstrItinData<IIC_IntCompare, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_IRACC, P440_LRACC]>,
                                  InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
                                  InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
                                  InstrStage<1, [P440_IWB, P440_JWB]>],
-                                [6, 4, 4],
+                                [2, 0, 0],
                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_IntDivW,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_IRACC]>,
                                  InstrStage<1, [P440_IEXE1]>,
                                  InstrStage<1, [P440_IEXE2]>,
                                  InstrStage<33, [P440_IWB]>],
-                                [40, 4, 4],
+                                [36, 0, 0],
                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_IntMFFS,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_IRACC]>,
                                  InstrStage<1, [P440_IEXE1]>,
                                  InstrStage<1, [P440_IEXE2]>,
                                  InstrStage<1, [P440_IWB]>],
-                                [7, 4, 4],
+                                [3, 0, 0],
                                 [P440_GPR_Bypass,
                                  P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_IntMTFSB0,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
@@ -148,7 +156,7 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_IEXE1]>,
                                  InstrStage<1, [P440_IEXE2]>,
                                  InstrStage<1, [P440_IWB]>],
-                                [7, 4, 4],
+                                [3, 0, 0],
                                 [P440_GPR_Bypass,
                                  P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_IntMulHW,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
@@ -156,28 +164,28 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_IEXE1]>,
                                  InstrStage<1, [P440_IEXE2]>,
                                  InstrStage<1, [P440_IWB]>],
-                                [8, 4, 4],
+                                [4, 0, 0],
                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_IntMulHWU,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_IRACC]>,
                                  InstrStage<1, [P440_IEXE1]>,
                                  InstrStage<1, [P440_IEXE2]>,
                                  InstrStage<1, [P440_IWB]>],
-                                [8, 4, 4],
+                                [4, 0, 0],
                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_IntMulLI,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_IRACC]>,
                                  InstrStage<1, [P440_IEXE1]>,
                                  InstrStage<1, [P440_IEXE2]>,
                                  InstrStage<1, [P440_IWB]>],
-                                [8, 4, 4],
+                                [4, 0, 0],
                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_IntRotate,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_IRACC, P440_LRACC]>,
                                  InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
                                  InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
                                  InstrStage<1, [P440_IWB, P440_JWB]>],
-                                [6, 4, 4],
+                                [2, 0, 0],
                                 [P440_GPR_Bypass,
                                  P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_IntShift,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
@@ -185,7 +193,7 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_IEXE1, P440_JEXE1]>,
                                  InstrStage<1, [P440_IEXE2, P440_JEXE2]>,
                                  InstrStage<1, [P440_IWB, P440_JWB]>],
-                                [6, 4, 4],
+                                [2, 0, 0],
                                 [P440_GPR_Bypass,
                                  P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_IntTrapW,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
@@ -193,140 +201,161 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_IEXE1]>,
                                  InstrStage<1, [P440_IEXE2]>,
                                  InstrStage<1, [P440_IWB]>],
-                                [6, 4],
+                                [2, 0],
                                 [P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_BrB,        [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_IRACC]>,
                                  InstrStage<1, [P440_IEXE1]>,
                                  InstrStage<1, [P440_IEXE2]>,
                                  InstrStage<1, [P440_IWB]>],
-                                [8, 4],
+                                [4, 0],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_BrCR,       [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_IRACC]>,
                                  InstrStage<1, [P440_IEXE1]>,
                                  InstrStage<1, [P440_IEXE2]>,
                                  InstrStage<1, [P440_IWB]>],
-                                [8, 4, 4],
+                                [4, 0, 0],
                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_BrMCR,      [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_IRACC]>,
                                  InstrStage<1, [P440_IEXE1]>,
                                  InstrStage<1, [P440_IEXE2]>,
                                  InstrStage<1, [P440_IWB]>],
-                                [8, 4, 4],
+                                [4, 0, 0],
                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_BrMCRX,     [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_IRACC]>,
                                  InstrStage<1, [P440_IEXE1]>,
                                  InstrStage<1, [P440_IEXE2]>,
                                  InstrStage<1, [P440_IWB]>],
-                                [8, 4, 4],
+                                [4, 0, 0],
                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStDCBA,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [8, 5],
+                                [1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStDCBF,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [8, 5],
+                                [1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStDCBI,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [8, 5],
+                                [1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStLoad,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<2, [P440_LWB]>],
-                                [9, 5],
+                                [5, 1, 1],
                                 [P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStLoadUpd,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<2, [P440_LWB]>],
-                                [9, 5],
+                                [5, 2, 1, 1],
+                                [P440_GPR_Bypass, P440_GPR_Bypass]>,
+  InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
+                                 InstrStage<1, [P440_LRACC]>,
+                                 InstrStage<1, [P440_AGEN]>,
+                                 InstrStage<1, [P440_CRD]>,
+                                 InstrStage<2, [P440_LWB]>],
+                                [5, 2, 1, 1],
                                 [P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStStore,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<2, [P440_LWB]>],
-                                [8, 5],
+                                [1, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<2, [P440_LWB]>],
-                                [8, 5],
+                                [2, 1, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStICBI,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [8, 5],
+                                [4, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStSTFD,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [8, 5, 5],
+                                [1, 1, 1],
                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStSTFDU,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [8, 5, 5],
+                                [2, 1, 1, 1],
                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStLFD,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<2, [P440_LWB]>],
-                                [9, 5, 5],
+                                [5, 1, 1],
                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStLFDU,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [9, 5, 5],
+                                [5, 2, 1, 1],
+                                [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
+  InstrItinData<IIC_LdStLFDUX,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
+                                 InstrStage<1, [P440_LRACC]>,
+                                 InstrStage<1, [P440_AGEN]>,
+                                 InstrStage<1, [P440_CRD]>,
+                                 InstrStage<1, [P440_LWB]>],
+                                [5, 2, 1, 1],
                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStLHA,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [8, 5],
+                                [4, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStLHAU,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [8, 5],
+                                [4, 1, 1],
+                                [NoBypass, P440_GPR_Bypass]>,
+  InstrItinData<IIC_LdStLHAUX,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
+                                 InstrStage<1, [P440_LRACC]>,
+                                 InstrStage<1, [P440_AGEN]>,
+                                 InstrStage<1, [P440_CRD]>,
+                                 InstrStage<1, [P440_LWB]>],
+                                [4, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStLMW,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [8, 5],
+                                [4, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStLWARX,  [InstrStage<1, [P440_DISS1]>,
                                  InstrStage<1, [P440_IRACC], 0>,
@@ -335,21 +364,28 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [8, 5],
+                                [4, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStSTD,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<2, [P440_LWB]>],
-                                [8, 5],
+                                [4, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStSTDU,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<2, [P440_LWB]>],
-                                [8, 5],
+                                [2, 1, 1, 1],
+                                [NoBypass, P440_GPR_Bypass]>,
+  InstrItinData<IIC_LdStSTDUX,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
+                                 InstrStage<1, [P440_LRACC]>,
+                                 InstrStage<1, [P440_AGEN]>,
+                                 InstrStage<1, [P440_CRD]>,
+                                 InstrStage<2, [P440_LWB]>],
+                                [2, 1, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStSTDCX,  [InstrStage<1, [P440_DISS1]>,
                                  InstrStage<1, [P440_IRACC], 0>,
@@ -358,7 +394,7 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [8, 5],
+                                [4, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStSTWCX,  [InstrStage<1, [P440_DISS1]>,
                                  InstrStage<1, [P440_IRACC], 0>,
@@ -367,7 +403,7 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [8, 5],
+                                [4, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStSync,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
@@ -395,21 +431,21 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_IEXE1]>,
                                  InstrStage<1, [P440_IEXE2]>,
                                  InstrStage<1, [P440_IWB]>],
-                                [6, 4],
+                                [2, 0],
                                 [P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_SprMTMSR,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_IRACC]>,
                                  InstrStage<1, [P440_IEXE1]>,
                                  InstrStage<1, [P440_IEXE2]>,
                                  InstrStage<1, [P440_IWB]>],
-                                [6, 4],
+                                [2, 0],
                                 [P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_SprMTSR,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_IRACC]>,
                                  InstrStage<1, [P440_IEXE1]>,
                                  InstrStage<1, [P440_IEXE2]>,
                                  InstrStage<3, [P440_IWB]>],
-                                [9, 4],
+                                [5, 0],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_SprTLBSYNC, [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_IRACC]>,
@@ -421,56 +457,56 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_IEXE1]>,
                                  InstrStage<1, [P440_IEXE2]>,
                                  InstrStage<1, [P440_IWB]>],
-                                [8, 4],
+                                [4, 0],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_SprMFMSR,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_IRACC]>,
                                  InstrStage<1, [P440_IEXE1]>,
                                  InstrStage<1, [P440_IEXE2]>,
                                  InstrStage<1, [P440_IWB]>],
-                                [7, 4],
+                                [3, 0],
                                 [P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_SprMFSPR,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_IRACC]>,
                                  InstrStage<1, [P440_IEXE1]>,
                                  InstrStage<1, [P440_IEXE2]>,
                                  InstrStage<3, [P440_IWB]>],
-                                [10, 4],
+                                [6, 0],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_SprMFTB,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_IRACC]>,
                                  InstrStage<1, [P440_IEXE1]>,
                                  InstrStage<1, [P440_IEXE2]>,
                                  InstrStage<3, [P440_IWB]>],
-                                [10, 4],
+                                [6, 0],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_SprMTSPR,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_IRACC]>,
                                  InstrStage<1, [P440_IEXE1]>,
                                  InstrStage<1, [P440_IEXE2]>,
                                  InstrStage<3, [P440_IWB]>],
-                                [10, 4],
+                                [6, 0],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_SprMTSRIN,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_IRACC]>,
                                  InstrStage<1, [P440_IEXE1]>,
                                  InstrStage<1, [P440_IEXE2]>,
                                  InstrStage<3, [P440_IWB]>],
-                                [10, 4],
+                                [6, 0],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_SprRFI,     [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_IRACC]>,
                                  InstrStage<1, [P440_IEXE1]>,
                                  InstrStage<1, [P440_IEXE2]>,
                                  InstrStage<1, [P440_IWB]>],
-                                [8, 4],
+                                [4, 0],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_SprSC,      [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_IRACC]>,
                                  InstrStage<1, [P440_IEXE1]>,
                                  InstrStage<1, [P440_IEXE2]>,
                                  InstrStage<1, [P440_IWB]>],
-                                [8, 4],
+                                [4, 0],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_FPGeneral,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_FRACC]>,
@@ -481,7 +517,7 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_FEXE5]>,
                                  InstrStage<1, [P440_FEXE6]>,
                                  InstrStage<1, [P440_FWB]>],
-                                [10, 4, 4],
+                                [6, 0, 0],
                                 [P440_FPR_Bypass,
                                  P440_FPR_Bypass, P440_FPR_Bypass]>,
   InstrItinData<IIC_FPAddSub,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
@@ -493,7 +529,7 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_FEXE5]>,
                                  InstrStage<1, [P440_FEXE6]>,
                                  InstrStage<1, [P440_FWB]>],
-                                [10, 4, 4],
+                                [6, 0, 0],
                                 [P440_FPR_Bypass,
                                  P440_FPR_Bypass, P440_FPR_Bypass]>,
   InstrItinData<IIC_FPCompare,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
@@ -505,7 +541,7 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_FEXE5]>,
                                  InstrStage<1, [P440_FEXE6]>,
                                  InstrStage<1, [P440_FWB]>],
-                                [10, 4, 4],
+                                [6, 0, 0],
                                 [P440_FPR_Bypass, P440_FPR_Bypass,
                                  P440_FPR_Bypass]>,
   InstrItinData<IIC_FPDivD,     [InstrStage<1, [P440_DISS1, P440_DISS2]>,
@@ -517,7 +553,7 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_FEXE5]>,
                                  InstrStage<1, [P440_FEXE6]>,
                                  InstrStage<25, [P440_FWB]>],
-                                [35, 4, 4],
+                                [31, 0, 0],
                                 [NoBypass, P440_FPR_Bypass, P440_FPR_Bypass]>,
   InstrItinData<IIC_FPDivS,     [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_FRACC]>,
@@ -528,7 +564,7 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_FEXE5]>,
                                  InstrStage<1, [P440_FEXE6]>,
                                  InstrStage<13, [P440_FWB]>],
-                                [23, 4, 4],
+                                [19, 0, 0],
                                 [NoBypass, P440_FPR_Bypass, P440_FPR_Bypass]>,
   InstrItinData<IIC_FPFused,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_FRACC]>,
@@ -539,7 +575,7 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_FEXE5]>,
                                  InstrStage<1, [P440_FEXE6]>,
                                  InstrStage<1, [P440_FWB]>],
-                                [10, 4, 4, 4],
+                                [6, 0, 0, 0],
                                 [P440_FPR_Bypass,
                                  P440_FPR_Bypass, P440_FPR_Bypass,
                                  P440_FPR_Bypass]>,
@@ -552,6 +588,20 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_FEXE5]>,
                                  InstrStage<1, [P440_FEXE6]>,
                                  InstrStage<1, [P440_FWB]>],
-                                [10, 4],
+                                [6, 0],
                                 [P440_FPR_Bypass, P440_FPR_Bypass]>
 ]>;
+
+// ===---------------------------------------------------------------------===//
+// PPC440 machine model for scheduling and other instruction cost heuristics.
+
+def PPC440Model : SchedMachineModel {
+  let IssueWidth = 2;  // 2 instructions are dispatched per cycle.
+  let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
+  let LoadLatency = 5; // Optimistic load latency assuming bypass.
+                       // This is overriden by OperandCycles if the
+                       // Itineraries are queried instead.
+
+  let Itineraries = PPC440Itineraries;
+}
+