R600/SI: Fix assertion from copying a TargetGlobalAddress

[oota-llvm.git] / lib / Target / PowerPC / PPCSchedule440.td

diff --git a/lib/Target/PowerPC/PPCSchedule440.td b/lib/Target/PowerPC/PPCSchedule440.td
index c8e620dd2ddca961f6090029517a117a1df47e9e..218fed248a31ff47a1376a814c660895b47c050f 100644 (file)
--- a/lib/Target/PowerPC/PPCSchedule440.td
+++ b/lib/Target/PowerPC/PPCSchedule440.td
@@ -228,70 +228,77 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [4, 1],
+                                [1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStDCBF,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [4, 1],
+                                [1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStDCBI,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [4, 1],
+                                [1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStLoad,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<2, [P440_LWB]>],
-                                [5, 1],
+                                [5, 1, 1],
                                 [P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStLoadUpd,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<2, [P440_LWB]>],
-                                [5, 1],
+                                [5, 2, 1, 1],
+                                [P440_GPR_Bypass, P440_GPR_Bypass]>,
+  InstrItinData<IIC_LdStLoadUpdX,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
+                                 InstrStage<1, [P440_LRACC]>,
+                                 InstrStage<1, [P440_AGEN]>,
+                                 InstrStage<1, [P440_CRD]>,
+                                 InstrStage<2, [P440_LWB]>],
+                                [5, 2, 1, 1],
                                 [P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStStore,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<2, [P440_LWB]>],
-                                [4, 1],
+                                [1, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStStoreUpd,[InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<2, [P440_LWB]>],
-                                [4, 1],
+                                [2, 1, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStICBI,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [4, 1],
+                                [4, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStSTFD,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [4, 1, 1],
+                                [1, 1, 1],
                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStSTFDU,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [4, 1, 1],
+                                [2, 1, 1, 1],
                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStLFD,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
@@ -305,28 +312,42 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [5, 1, 1],
+                                [5, 2, 1, 1],
+                                [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
+  InstrItinData<IIC_LdStLFDUX,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
+                                 InstrStage<1, [P440_LRACC]>,
+                                 InstrStage<1, [P440_AGEN]>,
+                                 InstrStage<1, [P440_CRD]>,
+                                 InstrStage<1, [P440_LWB]>],
+                                [5, 2, 1, 1],
                                 [NoBypass, P440_GPR_Bypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStLHA,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [4, 1],
+                                [4, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStLHAU,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [4, 1],
+                                [4, 1, 1],
+                                [NoBypass, P440_GPR_Bypass]>,
+  InstrItinData<IIC_LdStLHAUX,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
+                                 InstrStage<1, [P440_LRACC]>,
+                                 InstrStage<1, [P440_AGEN]>,
+                                 InstrStage<1, [P440_CRD]>,
+                                 InstrStage<1, [P440_LWB]>],
+                                [4, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStLMW,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [4, 1],
+                                [4, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStLWARX,  [InstrStage<1, [P440_DISS1]>,
                                  InstrStage<1, [P440_IRACC], 0>,
@@ -335,21 +356,28 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [4, 1],
+                                [4, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStSTD,    [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<2, [P440_LWB]>],
-                                [4, 1],
+                                [4, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStSTDU,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<2, [P440_LWB]>],
-                                [4, 1],
+                                [2, 1, 1, 1],
+                                [NoBypass, P440_GPR_Bypass]>,
+  InstrItinData<IIC_LdStSTDUX,  [InstrStage<1, [P440_DISS1, P440_DISS2]>,
+                                 InstrStage<1, [P440_LRACC]>,
+                                 InstrStage<1, [P440_AGEN]>,
+                                 InstrStage<1, [P440_CRD]>,
+                                 InstrStage<2, [P440_LWB]>],
+                                [2, 1, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStSTDCX,  [InstrStage<1, [P440_DISS1]>,
                                  InstrStage<1, [P440_IRACC], 0>,
@@ -358,7 +386,7 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [4, 1],
+                                [4, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStSTWCX,  [InstrStage<1, [P440_DISS1]>,
                                  InstrStage<1, [P440_IRACC], 0>,
@@ -367,7 +395,7 @@ def PPC440Itineraries : ProcessorItineraries<
                                  InstrStage<1, [P440_AGEN]>,
                                  InstrStage<1, [P440_CRD]>,
                                  InstrStage<1, [P440_LWB]>],
-                                [4, 1],
+                                [4, 1, 1],
                                 [NoBypass, P440_GPR_Bypass]>,
   InstrItinData<IIC_LdStSync,   [InstrStage<1, [P440_DISS1, P440_DISS2]>,
                                  InstrStage<1, [P440_LRACC]>,
@@ -555,3 +583,17 @@ def PPC440Itineraries : ProcessorItineraries<
                                 [6, 0],
                                 [P440_FPR_Bypass, P440_FPR_Bypass]>
 ]>;
+
+// ===---------------------------------------------------------------------===//
+// PPC440 machine model for scheduling and other instruction cost heuristics.
+
+def PPC440Model : SchedMachineModel {
+  let IssueWidth = 2;  // 2 instructions are dispatched per cycle.
+  let MinLatency = -1; // OperandCycles are interpreted as MinLatency.
+  let LoadLatency = 5; // Optimistic load latency assuming bypass.
+                       // This is overriden by OperandCycles if the
+                       // Itineraries are queried instead.
+
+  let Itineraries = PPC440Itineraries;
+}
+