-//===- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. -----*- tablegen -*-===//
-//
+//===-- PPCScheduleG4Plus.td - PPC G4+ Scheduling Defs. ----*- tablegen -*-===//
+//
// The LLVM Compiler Infrastructure
//
-// This file was developed by James M. Laskey and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
//===----------------------------------------------------------------------===//
//
// This file defines the itinerary class data for the G4+ (7450) processor.
//
//===----------------------------------------------------------------------===//
-def G4PlusItineraries : ProcessorItineraries<G4Plus, [
+def IU3 : FuncUnit; // integer unit 3 (7450 simple)
+def IU4 : FuncUnit; // integer unit 4 (7450 simple)
+
+def G4PlusItineraries : ProcessorItineraries<
+ [IU1, IU2, IU3, IU4, BPU, SLU, FPU1, VFPU, VIU1, VIU2, VPU], [], [
+ InstrItinData<IntSimple , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<IntGeneral , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<IntCompare , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
- InstrItinData<IntDivD , [InstrStage<0, [NoUnit]>]>,
InstrItinData<IntDivW , [InstrStage<23, [IU2]>]>,
InstrItinData<IntMFFS , [InstrStage<5, [FPU1]>]>,
InstrItinData<IntMFVSCR , [InstrStage<2, [VFPU]>]>,
InstrItinData<IntMTFSB0 , [InstrStage<5, [FPU1]>]>,
- InstrItinData<IntMTSRD , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<IntMulHD , [InstrStage<0, [NoUnit]>]>,
InstrItinData<IntMulHW , [InstrStage<4, [IU2]>]>,
InstrItinData<IntMulHWU , [InstrStage<4, [IU2]>]>,
InstrItinData<IntMulLI , [InstrStage<3, [IU2]>]>,
- InstrItinData<IntRFID , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<IntRotateD , [InstrStage<0, [NoUnit]>]>,
InstrItinData<IntRotate , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<IntShift , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
- InstrItinData<IntTrapD , [InstrStage<0, [NoUnit]>]>,
InstrItinData<IntTrapW , [InstrStage<2, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<BrB , [InstrStage<1, [BPU]>]>,
InstrItinData<BrCR , [InstrStage<2, [IU2]>]>,
InstrItinData<BrMCR , [InstrStage<2, [IU2]>]>,
InstrItinData<BrMCRX , [InstrStage<2, [IU2]>]>,
- InstrItinData<LdStDCBA , [InstrStage<0, [NoUnit]>]>,
InstrItinData<LdStDCBF , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStDCBI , [InstrStage<3, [SLU]>]>,
- InstrItinData<LdStDCBT , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStLoad , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStLoadUpd , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStStore , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStStoreUpd, [InstrStage<3, [SLU]>]>,
InstrItinData<LdStDSS , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStICBI , [InstrStage<3, [IU2]>]>,
- InstrItinData<LdStLBZUX , [InstrStage<3, [SLU]>]>,
- InstrItinData<LdStLD , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<LdStLDARX , [InstrStage<0, [NoUnit]>]>,
+ InstrItinData<LdStSTFD , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStSTFDU , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLFD , [InstrStage<4, [SLU]>]>,
InstrItinData<LdStLFDU , [InstrStage<4, [SLU]>]>,
InstrItinData<LdStLHA , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStLHAU , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLMW , [InstrStage<37, [SLU]>]>,
- InstrItinData<LdStLVEBX , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStLVecX , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLWA , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStLWARX , [InstrStage<3, [SLU]>]>,
- InstrItinData<LdStSLBIA , [InstrStage<0, [NoUnit]>]>,
- InstrItinData<LdStSLBIE , [InstrStage<0, [NoUnit]>]>,
InstrItinData<LdStSTD , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTDCX , [InstrStage<3, [SLU]>]>,
+ InstrItinData<LdStSTDU , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTVEBX , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSTWCX , [InstrStage<3, [SLU]>]>,
InstrItinData<LdStSync , [InstrStage<35, [SLU]>]>,
InstrItinData<SprRFI , [InstrStage<1, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<SprSC , [InstrStage<0, [IU1, IU2, IU3, IU4]>]>,
InstrItinData<FPGeneral , [InstrStage<5, [FPU1]>]>,
+ InstrItinData<FPAddSub , [InstrStage<5, [FPU1]>]>,
InstrItinData<FPCompare , [InstrStage<5, [FPU1]>]>,
InstrItinData<FPDivD , [InstrStage<35, [FPU1]>]>,
InstrItinData<FPDivS , [InstrStage<21, [FPU1]>]>,
InstrItinData<FPFused , [InstrStage<5, [FPU1]>]>,
InstrItinData<FPRes , [InstrStage<14, [FPU1]>]>,
- InstrItinData<FPSqrt , [InstrStage<0, [NoUnit]>]>,
InstrItinData<VecGeneral , [InstrStage<1, [VIU1]>]>,
InstrItinData<VecFP , [InstrStage<4, [VFPU]>]>,
InstrItinData<VecFPCompare, [InstrStage<2, [VFPU]>]>,