R600/SI: Fix assertion from copying a TargetGlobalAddress

[oota-llvm.git] / lib / Target / PowerPC / PPCScheduleG5.td

diff --git a/lib/Target/PowerPC/PPCScheduleG5.td b/lib/Target/PowerPC/PPCScheduleG5.td
index 2329e58b1ce6cba96b8178dcb5f12b790d555d83..a3b73ab4454fd1bf9014d9da4eef495d9d27542f 100644 (file)
--- a/lib/Target/PowerPC/PPCScheduleG5.td
+++ b/lib/Target/PowerPC/PPCScheduleG5.td
@@ -52,6 +52,7 @@ def G5Itineraries : ProcessorItineraries<
   InstrItinData<IIC_LdStDCBF    , [InstrStage<3, [G5_SLU]>]>,
   InstrItinData<IIC_LdStLoad    , [InstrStage<3, [G5_SLU]>]>,
   InstrItinData<IIC_LdStLoadUpd , [InstrStage<3, [G5_SLU]>]>,  
+  InstrItinData<IIC_LdStLoadUpdX, [InstrStage<3, [G5_SLU]>]>,  
   InstrItinData<IIC_LdStStore   , [InstrStage<3, [G5_SLU]>]>,
   InstrItinData<IIC_LdStStoreUpd, [InstrStage<3, [G5_SLU]>]>,  
   InstrItinData<IIC_LdStDSS     , [InstrStage<10, [G5_SLU]>]>,
@@ -60,11 +61,14 @@ def G5Itineraries : ProcessorItineraries<
   InstrItinData<IIC_LdStSTFDU   , [InstrStage<4, [G5_SLU]>]>,  
   InstrItinData<IIC_LdStLD      , [InstrStage<3, [G5_SLU]>]>,
   InstrItinData<IIC_LdStLDU     , [InstrStage<3, [G5_SLU]>]>,
+  InstrItinData<IIC_LdStLDUX    , [InstrStage<3, [G5_SLU]>]>,
   InstrItinData<IIC_LdStLDARX   , [InstrStage<11, [G5_SLU]>]>,
   InstrItinData<IIC_LdStLFD     , [InstrStage<3, [G5_SLU]>]>,
   InstrItinData<IIC_LdStLFDU    , [InstrStage<5, [G5_SLU]>]>,
+  InstrItinData<IIC_LdStLFDUX   , [InstrStage<5, [G5_SLU]>]>,
   InstrItinData<IIC_LdStLHA     , [InstrStage<5, [G5_SLU]>]>,
   InstrItinData<IIC_LdStLHAU    , [InstrStage<5, [G5_SLU]>]>,  
+  InstrItinData<IIC_LdStLHAUX   , [InstrStage<5, [G5_SLU]>]>,  
   InstrItinData<IIC_LdStLMW     , [InstrStage<64, [G5_SLU]>]>,
   InstrItinData<IIC_LdStLVecX   , [InstrStage<3, [G5_SLU]>]>,
   InstrItinData<IIC_LdStLWA     , [InstrStage<5, [G5_SLU]>]>,
@@ -73,6 +77,7 @@ def G5Itineraries : ProcessorItineraries<
   InstrItinData<IIC_LdStSLBIE   , [InstrStage<2, [G5_SLU]>]>,
   InstrItinData<IIC_LdStSTD     , [InstrStage<3, [G5_SLU]>]>,
   InstrItinData<IIC_LdStSTDU    , [InstrStage<3, [G5_SLU]>]>,
+  InstrItinData<IIC_LdStSTDUX   , [InstrStage<3, [G5_SLU]>]>,
   InstrItinData<IIC_LdStSTDCX   , [InstrStage<11, [G5_SLU]>]>,
   InstrItinData<IIC_LdStSTVEBX  , [InstrStage<5, [G5_SLU]>]>,
   InstrItinData<IIC_LdStSTWCX   , [InstrStage<11, [G5_SLU]>]>,
@@ -83,6 +88,7 @@ def G5Itineraries : ProcessorItineraries<
   InstrItinData<IIC_SprMTSR     , [InstrStage<3, [G5_SLU]>]>,
   InstrItinData<IIC_SprTLBSYNC  , [InstrStage<3, [G5_SLU]>]>,
   InstrItinData<IIC_SprMFCR     , [InstrStage<2, [G5_IU2]>]>,
+  InstrItinData<IIC_SprMFCRF    , [InstrStage<2, [G5_IU2]>]>,
   InstrItinData<IIC_SprMFMSR    , [InstrStage<3, [G5_IU2]>]>,
   InstrItinData<IIC_SprMFSPR    , [InstrStage<3, [G5_IU2]>]>,
   InstrItinData<IIC_SprMFTB     , [InstrStage<10, [G5_IU2]>]>,
@@ -95,7 +101,8 @@ def G5Itineraries : ProcessorItineraries<
   InstrItinData<IIC_FPDivS      , [InstrStage<33, [G5_FPU1, G5_FPU2]>]>,
   InstrItinData<IIC_FPFused     , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>,
   InstrItinData<IIC_FPRes       , [InstrStage<6, [G5_FPU1, G5_FPU2]>]>,
-  InstrItinData<IIC_FPSqrt      , [InstrStage<40, [G5_FPU1, G5_FPU2]>]>,
+  InstrItinData<IIC_FPSqrtD     , [InstrStage<40, [G5_FPU1, G5_FPU2]>]>,
+  InstrItinData<IIC_FPSqrtS     , [InstrStage<40, [G5_FPU1, G5_FPU2]>]>,
   InstrItinData<IIC_VecGeneral  , [InstrStage<2, [G5_VIU1]>]>,
   InstrItinData<IIC_VecFP       , [InstrStage<8, [G5_VFPU]>]>,
   InstrItinData<IIC_VecFPCompare, [InstrStage<2, [G5_VFPU]>]>,