-//===-- PowerPCTargetMachine.cpp - Define TargetMachine for PowerPC -------===//
-//
+//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
+//
// The LLVM Compiler Infrastructure
//
// This file was developed by the LLVM research group and is distributed under
// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+//
//===----------------------------------------------------------------------===//
-//
+//
+// Top-level implementation for the PowerPC target.
//
//===----------------------------------------------------------------------===//
-#include "PowerPCTargetMachine.h"
-#include "PowerPC.h"
+#include "PPC.h"
+#include "PPCFrameInfo.h"
+#include "PPCTargetMachine.h"
+#include "PPCJITInfo.h"
#include "llvm/Module.h"
#include "llvm/PassManager.h"
-#include "llvm/CodeGen/IntrinsicLowering.h"
+#include "llvm/Analysis/Verifier.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/CodeGen/Passes.h"
-#include "llvm/Target/TargetMachineImpls.h"
+#include "llvm/Target/TargetOptions.h"
+#include "llvm/Target/TargetMachineRegistry.h"
#include "llvm/Transforms/Scalar.h"
+#include "llvm/Support/CommandLine.h"
+#include <iostream>
using namespace llvm;
-// allocatePowerPCTargetMachine - Allocate and return a subclass of
-// TargetMachine that implements the PowerPC backend.
-//
-TargetMachine *llvm::allocatePowerPCTargetMachine(const Module &M,
- IntrinsicLowering *IL) {
- return new PowerPCTargetMachine(M, IL);
+namespace {
+ // Register the targets
+ RegisterTarget<PPCTargetMachine>
+ X("ppc32", " PowerPC");
}
-/// PowerPCTargetMachine ctor - Create an ILP32 architecture model
-///
-/// FIXME: Should double alignment be 8 bytes? Then we get a PtrAl != DoubleAl abort
-PowerPCTargetMachine::PowerPCTargetMachine(const Module &M,
- IntrinsicLowering *IL)
- : TargetMachine("PowerPC", IL, false, 4, 4, 4, 4, 4, 4, 4, 4),
- FrameInfo(TargetFrameInfo::StackGrowsDown, 16, -4), JITInfo(*this) {
+unsigned PPCTargetMachine::getJITMatchQuality() {
+#if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)
+ return 10;
+#else
+ return 0;
+#endif
+}
+
+unsigned PPCTargetMachine::getModuleMatchQuality(const Module &M) {
+ // We strongly match "powerpc-*".
+ std::string TT = M.getTargetTriple();
+ if (TT.size() >= 8 && std::string(TT.begin(), TT.begin()+8) == "powerpc-")
+ return 20;
+
+ if (M.getEndianness() == Module::BigEndian &&
+ M.getPointerSize() == Module::Pointer32)
+ return 10; // Weak match
+ else if (M.getEndianness() != Module::AnyEndianness ||
+ M.getPointerSize() != Module::AnyPointerSize)
+ return 0; // Match for some other target
+
+ return getJITMatchQuality()/2;
}
-/// addPassesToEmitAssembly - Add passes to the specified pass manager
-/// to implement a static compiler for this target.
+PPCTargetMachine::PPCTargetMachine(const Module &M, const std::string &FS)
+: TargetMachine("PowerPC", false, 4, 4, 4, 4, 4, 4, 2, 1, 1),
+ Subtarget(M, FS), FrameInfo(*this, false), JITInfo(*this),
+ TLInfo(*this), InstrItins(Subtarget.getInstrItineraryData()) {
+ if (TargetDefault == PPCTarget) {
+ if (Subtarget.isAIX()) PPCTarget = TargetAIX;
+ if (Subtarget.isDarwin()) PPCTarget = TargetDarwin;
+ }
+ if (getRelocationModel() == Reloc::Default)
+ if (Subtarget.isDarwin())
+ setRelocationModel(Reloc::DynamicNoPIC);
+ else
+ setRelocationModel(Reloc::PIC);
+}
+
+/// addPassesToEmitFile - Add passes to the specified pass manager to implement
+/// a static compiler for this target.
///
-bool PowerPCTargetMachine::addPassesToEmitAssembly(PassManager &PM,
- std::ostream &Out) {
+bool PPCTargetMachine::addPassesToEmitFile(PassManager &PM,
+ std::ostream &Out,
+ CodeGenFileType FileType,
+ bool Fast) {
+ if (FileType != TargetMachine::AssemblyFile) return true;
+
+ // Run loop strength reduction before anything else.
+ if (!Fast) PM.add(createLoopStrengthReducePass(&TLInfo));
+
// FIXME: Implement efficient support for garbage collection intrinsics.
PM.add(createLowerGCPass());
// FIXME: Implement the invoke/unwind instructions!
PM.add(createLowerInvokePass());
-
- // FIXME: The code generator does not properly handle functions with
- // unreachable basic blocks.
- PM.add(createCFGSimplificationPass());
+
+ // Clean up after other passes, e.g. merging critical edges.
+ if (!Fast) PM.add(createCFGSimplificationPass());
// FIXME: Implement the switch instruction in the instruction selector!
PM.add(createLowerSwitchPass());
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
+ // Make sure that no unreachable blocks are instruction selected.
+ PM.add(createUnreachableBlockEliminationPass());
- PM.add(createPPCSimpleInstructionSelector(*this));
+ // Install an instruction selector.
+ PM.add(createPPCISelDag(*this));
if (PrintMachineCode)
PM.add(createMachineFunctionPrinterPass(&std::cerr));
PM.add(createMachineFunctionPrinterPass(&std::cerr));
PM.add(createPrologEpilogCodeInserter());
- PM.add(createPPCCodePrinterPass(Out, *this));
+
+ // Must run branch selection immediately preceding the asm printer
+ PM.add(createPPCBranchSelectionPass());
+
+ // Decide which asm printer to use. If the user has not specified one on
+ // the command line, choose whichever one matches the default (current host).
+ switch (PPCTarget) {
+ case TargetAIX:
+ PM.add(createAIXAsmPrinter(Out, *this));
+ break;
+ case TargetDefault:
+ case TargetDarwin:
+ PM.add(createDarwinAsmPrinter(Out, *this));
+ break;
+ }
+
PM.add(createMachineCodeDeleter());
return false;
}
-/// addPassesToJITCompile - Add passes to the specified pass manager to
-/// implement a fast dynamic compiler for this target.
-///
-void PowerPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
+void PPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
+ // The JIT should use dynamic-no-pic relocation model.
+ TM.setRelocationModel(Reloc::DynamicNoPIC);
+
+ // Run loop strength reduction before anything else.
+ PM.add(createLoopStrengthReducePass(TM.getTargetLowering()));
+
// FIXME: Implement efficient support for garbage collection intrinsics.
PM.add(createLowerGCPass());
// FIXME: Implement the invoke/unwind instructions!
PM.add(createLowerInvokePass());
- // FIXME: The code generator does not properly handle functions with
- // unreachable basic blocks.
+ // Clean up after other passes, e.g. merging critical edges.
PM.add(createCFGSimplificationPass());
// FIXME: Implement the switch instruction in the instruction selector!
PM.add(createLowerSwitchPass());
- PM.add(createPPCSimpleInstructionSelector(TM));
+ // Make sure that no unreachable blocks are instruction selected.
+ PM.add(createUnreachableBlockEliminationPass());
+
+ // Install an instruction selector.
+ PM.add(createPPCISelDag(TM));
+
PM.add(createRegisterAllocator());
PM.add(createPrologEpilogCodeInserter());
+
+ // Must run branch selection immediately preceding the asm printer
+ PM.add(createPPCBranchSelectionPass());
+
+ if (PrintMachineCode)
+ PM.add(createMachineFunctionPrinterPass(&std::cerr));
}
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