-//===-- PowerPCTargetMachine.cpp - Define TargetMachine for PowerPC -------===//
-//
+//===-- PPCTargetMachine.cpp - Define TargetMachine for PowerPC -----------===//
+//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-//
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
//===----------------------------------------------------------------------===//
-//
+//
+// Top-level implementation for the PowerPC target.
//
//===----------------------------------------------------------------------===//
-#include "PowerPCTargetMachine.h"
-#include "PowerPC.h"
-#include "llvm/Module.h"
+#include "PPC.h"
+#include "PPCTargetMachine.h"
#include "llvm/PassManager.h"
-#include "llvm/CodeGen/IntrinsicLowering.h"
-#include "llvm/CodeGen/MachineFunction.h"
+#include "llvm/MC/MCStreamer.h"
#include "llvm/CodeGen/Passes.h"
-#include "llvm/Target/TargetMachineImpls.h"
-#include "llvm/Transforms/Scalar.h"
+#include "llvm/Target/TargetOptions.h"
+#include "llvm/Support/FormattedStream.h"
+#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
-// allocatePowerPCTargetMachine - Allocate and return a subclass of
-// TargetMachine that implements the PowerPC backend.
-//
-TargetMachine *llvm::allocatePowerPCTargetMachine(const Module &M,
- IntrinsicLowering *IL) {
- return new PowerPCTargetMachine(M, IL);
+extern "C" void LLVMInitializePowerPCTarget() {
+ // Register the targets
+ RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
+ RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
}
-/// PowerPCTargetMachine ctor - Create an ILP32 architecture model
-///
-/// FIXME: Should double alignment be 8 bytes? Then we get a PtrAl != DoubleAl
-/// abort
-PowerPCTargetMachine::PowerPCTargetMachine(const Module &M,
- IntrinsicLowering *IL)
- : TargetMachine("PowerPC", IL, false, 4, 4, 4, 4, 4, 4, 4, 4),
- FrameInfo(TargetFrameInfo::StackGrowsDown, 16, -4), JITInfo(*this) {
+PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
+ StringRef CPU, StringRef FS,
+ const TargetOptions &Options,
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL,
+ bool is64Bit)
+ : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
+ Subtarget(TT, CPU, FS, is64Bit),
+ DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
+ FrameLowering(Subtarget), JITInfo(*this, is64Bit),
+ TLInfo(*this), TSInfo(*this),
+ InstrItins(Subtarget.getInstrItineraryData()) {
}
-/// addPassesToEmitAssembly - Add passes to the specified pass manager
-/// to implement a static compiler for this target.
-///
-bool PowerPCTargetMachine::addPassesToEmitAssembly(PassManager &PM,
- std::ostream &Out) {
- // FIXME: Implement efficient support for garbage collection intrinsics.
- PM.add(createLowerGCPass());
+void PPC32TargetMachine::anchor() { }
- // FIXME: Implement the invoke/unwind instructions!
- PM.add(createLowerInvokePass());
+PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
+ StringRef CPU, StringRef FS,
+ const TargetOptions &Options,
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
+ : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
+}
- // FIXME: Implement the switch instruction in the instruction selector!
- PM.add(createLowerSwitchPass());
+void PPC64TargetMachine::anchor() { }
+
+PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
+ StringRef CPU, StringRef FS,
+ const TargetOptions &Options,
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
+ : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
+}
- PM.add(createLowerConstantExpressionsPass());
- PM.add(createPPCSimpleInstructionSelector(*this));
+//===----------------------------------------------------------------------===//
+// Pass Pipeline Configuration
+//===----------------------------------------------------------------------===//
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
+namespace {
+/// PPC Code Generator Pass Configuration Options.
+class PPCPassConfig : public TargetPassConfig {
+public:
+ PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
+ : TargetPassConfig(TM, PM) {}
- PM.add(createRegisterAllocator());
+ PPCTargetMachine &getPPCTargetMachine() const {
+ return getTM<PPCTargetMachine>();
+ }
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
+ virtual bool addInstSelector();
+ virtual bool addPreEmitPass();
+};
+} // namespace
- PM.add(createPrologEpilogCodeInserter());
- PM.add(createPPCCodePrinterPass(Out, *this));
- PM.add(createMachineCodeDeleter());
+TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
+ TargetPassConfig *PassConfig = new PPCPassConfig(this, PM);
+
+ // Override this for PowerPC. Tail merging happily breaks up instruction issue
+ // groups, which typically degrades performance.
+ PassConfig->setEnableTailMerge(false);
+
+ return PassConfig;
+}
+
+bool PPCPassConfig::addInstSelector() {
+ // Install an instruction selector.
+ PM.add(createPPCISelDag(getPPCTargetMachine()));
return false;
}
-/// addPassesToJITCompile - Add passes to the specified pass manager to
-/// implement a fast dynamic compiler for this target.
-///
-void PowerPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
- // FIXME: Implement efficient support for garbage collection intrinsics.
- PM.add(createLowerGCPass());
+bool PPCPassConfig::addPreEmitPass() {
+ // Must run branch selection immediately preceding the asm printer.
+ PM.add(createPPCBranchSelectionPass());
+ return false;
+}
- // FIXME: Implement the invoke/unwind instructions!
- PM.add(createLowerInvokePass());
+bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
+ JITCodeEmitter &JCE) {
+ // FIXME: This should be moved to TargetJITInfo!!
+ if (Subtarget.isPPC64())
+ // Temporary workaround for the inability of PPC64 JIT to handle jump
+ // tables.
+ Options.DisableJumpTables = true;
- // FIXME: Implement the switch instruction in the instruction selector!
- PM.add(createLowerSwitchPass());
+ // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
+ // writing?
+ Subtarget.SetJITMode();
- PM.add(createLowerConstantExpressionsPass());
+ // Machine code emitter pass for PowerPC.
+ PM.add(createPPCJITCodeEmitterPass(*this, JCE));
- PM.add(createPPCSimpleInstructionSelector(TM));
- PM.add(createRegisterAllocator());
- PM.add(createPrologEpilogCodeInserter());
+ return false;
}
-
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