//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
//===----------------------------------------------------------------------===//
#include "PPC.h"
-#include "PPCFrameInfo.h"
#include "PPCTargetMachine.h"
-#include "PPCJITInfo.h"
-#include "llvm/Module.h"
#include "llvm/PassManager.h"
-#include "llvm/Analysis/Verifier.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/Passes.h"
+#include "llvm/MC/MCStreamer.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/Target/TargetMachineRegistry.h"
-#include "llvm/Transforms/Scalar.h"
-#include "llvm/Support/CommandLine.h"
-#include <iostream>
+#include "llvm/Support/FormattedStream.h"
+#include "llvm/Support/TargetRegistry.h"
using namespace llvm;
-namespace {
+extern "C" void LLVMInitializePowerPCTarget() {
// Register the targets
- RegisterTarget<PPCTargetMachine>
- X("ppc32", " PowerPC");
+ RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
+ RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
}
-unsigned PPCTargetMachine::getJITMatchQuality() {
-#if defined(__POWERPC__) || defined (__ppc__) || defined(_POWER)
- return 10;
-#else
- return 0;
-#endif
+PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
+ StringRef CPU, StringRef FS,
+ Reloc::Model RM, CodeModel::Model CM,
+ bool is64Bit)
+ : LLVMTargetMachine(T, TT, CPU, FS, RM, CM),
+ Subtarget(TT, CPU, FS, is64Bit),
+ DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
+ FrameLowering(Subtarget), JITInfo(*this, is64Bit),
+ TLInfo(*this), TSInfo(*this),
+ InstrItins(Subtarget.getInstrItineraryData()) {
}
-unsigned PPCTargetMachine::getModuleMatchQuality(const Module &M) {
- // We strongly match "powerpc-*".
- std::string TT = M.getTargetTriple();
- if (TT.size() >= 8 && std::string(TT.begin(), TT.begin()+8) == "powerpc-")
- return 20;
-
- if (M.getEndianness() == Module::BigEndian &&
- M.getPointerSize() == Module::Pointer32)
- return 10; // Weak match
- else if (M.getEndianness() != Module::AnyEndianness ||
- M.getPointerSize() != Module::AnyPointerSize)
- return 0; // Match for some other target
-
- return getJITMatchQuality()/2;
-}
+/// Override this for PowerPC. Tail merging happily breaks up instruction issue
+/// groups, which typically degrades performance.
+bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; }
-PPCTargetMachine::PPCTargetMachine(const Module &M, const std::string &FS)
-: TargetMachine("PowerPC"),
- DataLayout(std::string("PowerPC"), std::string("E-p:32:32-d:64:32-l:64:32")),
- Subtarget(M, FS), FrameInfo(*this, false), JITInfo(*this),
- TLInfo(*this), InstrItins(Subtarget.getInstrItineraryData()) {
- if (TargetDefault == PPCTarget) {
- if (Subtarget.isAIX()) PPCTarget = TargetAIX;
- if (Subtarget.isDarwin()) PPCTarget = TargetDarwin;
- }
- if (getRelocationModel() == Reloc::Default)
- if (Subtarget.isDarwin())
- setRelocationModel(Reloc::DynamicNoPIC);
- else
- setRelocationModel(Reloc::PIC);
+PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
+ StringRef CPU, StringRef FS,
+ Reloc::Model RM, CodeModel::Model CM)
+ : PPCTargetMachine(T, TT, CPU, FS, RM, CM, false) {
}
-/// addPassesToEmitFile - Add passes to the specified pass manager to implement
-/// a static compiler for this target.
-///
-bool PPCTargetMachine::addPassesToEmitFile(PassManager &PM,
- std::ostream &Out,
- CodeGenFileType FileType,
- bool Fast) {
- if (FileType != TargetMachine::AssemblyFile) return true;
-
- // Run loop strength reduction before anything else.
- if (!Fast) PM.add(createLoopStrengthReducePass(&TLInfo));
- // FIXME: Implement efficient support for garbage collection intrinsics.
- PM.add(createLowerGCPass());
+PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
+ StringRef CPU, StringRef FS,
+ Reloc::Model RM, CodeModel::Model CM)
+ : PPCTargetMachine(T, TT, CPU, FS, RM, CM, true) {
+}
- // FIXME: Implement the invoke/unwind instructions!
- PM.add(createLowerInvokePass());
-
- // Clean up after other passes, e.g. merging critical edges.
- if (!Fast) PM.add(createCFGSimplificationPass());
- // Make sure that no unreachable blocks are instruction selected.
- PM.add(createUnreachableBlockEliminationPass());
+//===----------------------------------------------------------------------===//
+// Pass Pipeline Configuration
+//===----------------------------------------------------------------------===//
+bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
// Install an instruction selector.
PM.add(createPPCISelDag(*this));
+ return false;
+}
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
-
- PM.add(createRegisterAllocator());
-
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
-
- PM.add(createPrologEpilogCodeInserter());
-
- // Must run branch selection immediately preceding the asm printer
+bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel) {
+ // Must run branch selection immediately preceding the asm printer.
PM.add(createPPCBranchSelectionPass());
-
- // Decide which asm printer to use. If the user has not specified one on
- // the command line, choose whichever one matches the default (current host).
- switch (PPCTarget) {
- case TargetAIX:
- PM.add(createAIXAsmPrinter(Out, *this));
- break;
- case TargetDefault:
- case TargetDarwin:
- PM.add(createDarwinAsmPrinter(Out, *this));
- break;
- }
-
- PM.add(createMachineCodeDeleter());
return false;
}
-void PPCJITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
- // The JIT should use the static relocation model.
- TM.setRelocationModel(Reloc::Static);
-
- // Run loop strength reduction before anything else.
- PM.add(createLoopStrengthReducePass(TM.getTargetLowering()));
-
- // FIXME: Implement efficient support for garbage collection intrinsics.
- PM.add(createLowerGCPass());
-
- // FIXME: Implement the invoke/unwind instructions!
- PM.add(createLowerInvokePass());
-
- // Clean up after other passes, e.g. merging critical edges.
- PM.add(createCFGSimplificationPass());
-
- // Make sure that no unreachable blocks are instruction selected.
- PM.add(createUnreachableBlockEliminationPass());
-
- // Install an instruction selector.
- PM.add(createPPCISelDag(TM));
-
- PM.add(createRegisterAllocator());
- PM.add(createPrologEpilogCodeInserter());
-
- // Must run branch selection immediately preceding the asm printer
- PM.add(createPPCBranchSelectionPass());
+bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
+ CodeGenOpt::Level OptLevel,
+ JITCodeEmitter &JCE) {
+ // FIXME: This should be moved to TargetJITInfo!!
+ if (Subtarget.isPPC64())
+ // Temporary workaround for the inability of PPC64 JIT to handle jump
+ // tables.
+ DisableJumpTables = true;
+
+ // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
+ // writing?
+ Subtarget.SetJITMode();
+
+ // Machine code emitter pass for PowerPC.
+ PM.add(createPPCJITCodeEmitterPass(*this, JCE));
- if (PrintMachineCode)
- PM.add(createMachineFunctionPrinterPass(&std::cerr));
+ return false;
}
-
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