//
//===----------------------------------------------------------------------===//
-#include "PPC.h"
-#include "PPCTargetAsmInfo.h"
#include "PPCTargetMachine.h"
-#include "llvm/Module.h"
+#include "PPC.h"
+#include "llvm/CodeGen/Passes.h"
+#include "llvm/MC/MCStreamer.h"
#include "llvm/PassManager.h"
-#include "llvm/Target/TargetMachineRegistry.h"
-#include "llvm/Target/TargetOptions.h"
+#include "llvm/Support/CommandLine.h"
#include "llvm/Support/FormattedStream.h"
+#include "llvm/Support/TargetRegistry.h"
+#include "llvm/Target/TargetOptions.h"
using namespace llvm;
-/// PowerPCTargetMachineModule - Note that this is used on hosts that
-/// cannot link in a library unless there are references into the
-/// library. In particular, it seems that it is not possible to get
-/// things to work on Win32 without this. Though it is unused, do not
-/// remove it.
-extern "C" int PowerPCTargetMachineModule;
-int PowerPCTargetMachineModule = 0;
-
-// Register the targets
-extern Target ThePPC32Target;
-static RegisterTarget<PPC32TargetMachine>
-X(ThePPC32Target, "ppc32", "PowerPC 32");
-
-extern Target ThePPC64Target;
-static RegisterTarget<PPC64TargetMachine>
-Y(ThePPC64Target, "ppc64", "PowerPC 64");
-
-// Force static initialization.
-extern "C" void LLVMInitializePowerPCTarget() { }
-
-// No assembler printer by default
-PPCTargetMachine::AsmPrinterCtorFn PPCTargetMachine::AsmPrinterCtor = 0;
-
-const TargetAsmInfo *PPCTargetMachine::createTargetAsmInfo() const {
- if (Subtarget.isDarwin())
- return new PPCDarwinTargetAsmInfo(*this);
- else
- return new PPCLinuxTargetAsmInfo(*this);
+static cl::
+opt<bool> DisableCTRLoops("disable-ppc-ctrloops", cl::Hidden,
+ cl::desc("Disable CTR loops for PPC"));
+
+extern "C" void LLVMInitializePowerPCTarget() {
+ // Register the targets
+ RegisterTargetMachine<PPC32TargetMachine> A(ThePPC32Target);
+ RegisterTargetMachine<PPC64TargetMachine> B(ThePPC64Target);
}
-PPCTargetMachine::PPCTargetMachine(const Target&T, const Module &M,
- const std::string &FS, bool is64Bit)
- : LLVMTargetMachine(T),
- Subtarget(*this, M, FS, is64Bit),
- DataLayout(Subtarget.getTargetDataString()), InstrInfo(*this),
- FrameInfo(*this, is64Bit), JITInfo(*this, is64Bit), TLInfo(*this),
- InstrItins(Subtarget.getInstrItineraryData()), MachOWriterInfo(*this) {
-
- if (getRelocationModel() == Reloc::Default) {
- if (Subtarget.isDarwin())
- setRelocationModel(Reloc::DynamicNoPIC);
- else
- setRelocationModel(Reloc::Static);
- }
+PPCTargetMachine::PPCTargetMachine(const Target &T, StringRef TT,
+ StringRef CPU, StringRef FS,
+ const TargetOptions &Options,
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL,
+ bool is64Bit)
+ : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
+ Subtarget(TT, CPU, FS, is64Bit),
+ DL(Subtarget.getDataLayoutString()), InstrInfo(*this),
+ FrameLowering(Subtarget), JITInfo(*this, is64Bit),
+ TLInfo(*this), TSInfo(*this),
+ InstrItins(Subtarget.getInstrItineraryData()) {
+
+ // The binutils for the BG/P are too old for CFI.
+ if (Subtarget.isBGP())
+ setMCUseCFI(false);
}
-/// Override this for PowerPC. Tail merging happily breaks up instruction issue
-/// groups, which typically degrades performance.
-bool PPCTargetMachine::getEnableTailMergeDefault() const { return false; }
+void PPC32TargetMachine::anchor() { }
-PPC32TargetMachine::PPC32TargetMachine(const Target &T, const Module &M,
- const std::string &FS)
- : PPCTargetMachine(T, M, FS, false) {
+PPC32TargetMachine::PPC32TargetMachine(const Target &T, StringRef TT,
+ StringRef CPU, StringRef FS,
+ const TargetOptions &Options,
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
+ : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
}
+void PPC64TargetMachine::anchor() { }
-PPC64TargetMachine::PPC64TargetMachine(const Target &T, const Module &M,
- const std::string &FS)
- : PPCTargetMachine(T, M, FS, true) {
+PPC64TargetMachine::PPC64TargetMachine(const Target &T, StringRef TT,
+ StringRef CPU, StringRef FS,
+ const TargetOptions &Options,
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL)
+ : PPCTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
}
// Pass Pipeline Configuration
//===----------------------------------------------------------------------===//
-bool PPCTargetMachine::addInstSelector(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel) {
- // Install an instruction selector.
- PM.add(createPPCISelDag(*this));
- return false;
-}
+namespace {
+/// PPC Code Generator Pass Configuration Options.
+class PPCPassConfig : public TargetPassConfig {
+public:
+ PPCPassConfig(PPCTargetMachine *TM, PassManagerBase &PM)
+ : TargetPassConfig(TM, PM) {}
-bool PPCTargetMachine::addPreEmitPass(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel) {
- // Must run branch selection immediately preceding the asm printer.
- PM.add(createPPCBranchSelectionPass());
- return false;
-}
+ PPCTargetMachine &getPPCTargetMachine() const {
+ return getTM<PPCTargetMachine>();
+ }
-bool PPCTargetMachine::addAssemblyEmitter(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel,
- bool Verbose,
- formatted_raw_ostream &Out) {
- assert(AsmPrinterCtor && "AsmPrinter was not linked in");
- if (AsmPrinterCtor)
- PM.add(AsmPrinterCtor(Out, *this, Verbose));
+ virtual bool addPreRegAlloc();
+ virtual bool addInstSelector();
+ virtual bool addPreEmitPass();
+};
+} // namespace
- return false;
+TargetPassConfig *PPCTargetMachine::createPassConfig(PassManagerBase &PM) {
+ return new PPCPassConfig(this, PM);
}
-bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel,
- bool DumpAsm, MachineCodeEmitter &MCE) {
- // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
- // FIXME: This should be moved to TargetJITInfo!!
- if (Subtarget.isPPC64()) {
- // We use PIC codegen in ppc64 mode, because otherwise we'd have to use many
- // instructions to materialize arbitrary global variable + function +
- // constant pool addresses.
- setRelocationModel(Reloc::PIC_);
- // Temporary workaround for the inability of PPC64 JIT to handle jump
- // tables.
- DisableJumpTables = true;
- } else {
- setRelocationModel(Reloc::Static);
- }
-
- // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
- // writing?
- Subtarget.SetJITMode();
-
- // Machine code emitter pass for PowerPC.
- PM.add(createPPCCodeEmitterPass(*this, MCE));
- if (DumpAsm)
- addAssemblyEmitter(PM, OptLevel, true, ferrs());
+bool PPCPassConfig::addPreRegAlloc() {
+ if (!DisableCTRLoops && getOptLevel() != CodeGenOpt::None)
+ addPass(createPPCCTRLoops());
return false;
}
-bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel,
- bool DumpAsm, JITCodeEmitter &JCE) {
- // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
- // FIXME: This should be moved to TargetJITInfo!!
- if (Subtarget.isPPC64()) {
- // We use PIC codegen in ppc64 mode, because otherwise we'd have to use many
- // instructions to materialize arbitrary global variable + function +
- // constant pool addresses.
- setRelocationModel(Reloc::PIC_);
- // Temporary workaround for the inability of PPC64 JIT to handle jump
- // tables.
- DisableJumpTables = true;
- } else {
- setRelocationModel(Reloc::Static);
- }
-
- // Inform the subtarget that we are in JIT mode. FIXME: does this break macho
- // writing?
- Subtarget.SetJITMode();
-
- // Machine code emitter pass for PowerPC.
- PM.add(createPPCJITCodeEmitterPass(*this, JCE));
- if (DumpAsm)
- addAssemblyEmitter(PM, OptLevel, true, ferrs());
+bool PPCPassConfig::addInstSelector() {
+ // Install an instruction selector.
+ addPass(createPPCISelDag(getPPCTargetMachine()));
+ return false;
+}
+bool PPCPassConfig::addPreEmitPass() {
+ // Must run branch selection immediately preceding the asm printer.
+ addPass(createPPCBranchSelectionPass());
return false;
}
bool PPCTargetMachine::addCodeEmitter(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel,
- bool DumpAsm, ObjectCodeEmitter &OCE) {
- // The JIT should use the static relocation model in ppc32 mode, PIC in ppc64.
- // FIXME: This should be moved to TargetJITInfo!!
- if (Subtarget.isPPC64()) {
- // We use PIC codegen in ppc64 mode, because otherwise we'd have to use many
- // instructions to materialize arbitrary global variable + function +
- // constant pool addresses.
- setRelocationModel(Reloc::PIC_);
- // Temporary workaround for the inability of PPC64 JIT to handle jump
- // tables.
- DisableJumpTables = true;
- } else {
- setRelocationModel(Reloc::Static);
- }
-
+ JITCodeEmitter &JCE) {
// Inform the subtarget that we are in JIT mode. FIXME: does this break macho
// writing?
Subtarget.SetJITMode();
-
- // Machine code emitter pass for PowerPC.
- PM.add(createPPCObjectCodeEmitterPass(*this, OCE));
- if (DumpAsm)
- addAssemblyEmitter(PM, OptLevel, true, ferrs());
-
- return false;
-}
-bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel,
- bool DumpAsm,
- MachineCodeEmitter &MCE) {
- // Machine code emitter pass for PowerPC.
- PM.add(createPPCCodeEmitterPass(*this, MCE));
- if (DumpAsm)
- addAssemblyEmitter(PM, OptLevel, true, ferrs());
-
- return false;
-}
-
-bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel,
- bool DumpAsm,
- JITCodeEmitter &JCE) {
// Machine code emitter pass for PowerPC.
PM.add(createPPCJITCodeEmitterPass(*this, JCE));
- if (DumpAsm)
- addAssemblyEmitter(PM, OptLevel, true, ferrs());
return false;
}
-bool PPCTargetMachine::addSimpleCodeEmitter(PassManagerBase &PM,
- CodeGenOpt::Level OptLevel,
- bool DumpAsm,
- ObjectCodeEmitter &OCE) {
- // Machine code emitter pass for PowerPC.
- PM.add(createPPCObjectCodeEmitterPass(*this, OCE));
- if (DumpAsm)
- addAssemblyEmitter(PM, OptLevel, true, ferrs());
-
- return false;
+void PPCTargetMachine::addAnalysisPasses(PassManagerBase &PM) {
+ // Add first the target-independent BasicTTI pass, then our PPC pass. This
+ // allows the PPC pass to delegate to the target independent layer when
+ // appropriate.
+ PM.add(createBasicTargetTransformInfoPass(getTargetLowering()));
+ PM.add(createPPCTargetTransformInfoPass(this));
}
-