-//===-- PPCTargetMachine.h - Define TargetMachine for PowerPC -----*- C++ -*-=//
+//===-- PPCTargetMachine.h - Define TargetMachine for PowerPC ---*- C++ -*-===//
//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
#ifndef PPC_TARGETMACHINE_H
#define PPC_TARGETMACHINE_H
-#include "PPCFrameInfo.h"
-#include "PPCSubtarget.h"
-#include "PPCJITInfo.h"
#include "PPCInstrInfo.h"
-#include "PPCISelLowering.h"
-#include "PPCMachOWriterInfo.h"
+#include "PPCSubtarget.h"
+#include "llvm/IR/DataLayout.h"
#include "llvm/Target/TargetMachine.h"
-#include "llvm/Target/TargetData.h"
namespace llvm {
-class PassManager;
-class GlobalValue;
/// PPCTargetMachine - Common code between 32-bit and 64-bit PowerPC targets.
///
class PPCTargetMachine : public LLVMTargetMachine {
PPCSubtarget Subtarget;
- const TargetData DataLayout; // Calculates type size & alignment
- PPCInstrInfo InstrInfo;
- PPCFrameInfo FrameInfo;
- PPCJITInfo JITInfo;
- PPCTargetLowering TLInfo;
- InstrItineraryData InstrItins;
- PPCMachOWriterInfo MachOWriterInfo;
-protected:
- virtual const TargetAsmInfo *createTargetAsmInfo() const;
-
public:
- PPCTargetMachine(const Module &M, const std::string &FS, bool is64Bit);
+ PPCTargetMachine(const Target &T, StringRef TT,
+ StringRef CPU, StringRef FS, const TargetOptions &Options,
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL, bool is64Bit);
+
+ const PPCSubtarget *getSubtargetImpl() const override { return &Subtarget; }
- virtual const PPCInstrInfo *getInstrInfo() const { return &InstrInfo; }
- virtual const TargetFrameInfo *getFrameInfo() const { return &FrameInfo; }
- virtual TargetJITInfo *getJITInfo() { return &JITInfo; }
- virtual PPCTargetLowering *getTargetLowering() const {
- return const_cast<PPCTargetLowering*>(&TLInfo);
- }
- virtual const MRegisterInfo *getRegisterInfo() const {
- return &InstrInfo.getRegisterInfo();
- }
-
- virtual const TargetData *getTargetData() const { return &DataLayout; }
- virtual const PPCSubtarget *getSubtargetImpl() const { return &Subtarget; }
- virtual const InstrItineraryData getInstrItineraryData() const {
- return InstrItins;
- }
- virtual const PPCMachOWriterInfo *getMachOWriterInfo() const {
- return &MachOWriterInfo;
- }
-
// Pass Pipeline Configuration
- virtual bool addInstSelector(FunctionPassManager &PM, bool Fast);
- virtual bool addPreEmitPass(FunctionPassManager &PM, bool Fast);
- virtual bool addAssemblyEmitter(FunctionPassManager &PM, bool Fast,
- std::ostream &Out);
- virtual bool addCodeEmitter(FunctionPassManager &PM, bool Fast,
- bool DumpAsm, MachineCodeEmitter &MCE);
- virtual bool addSimpleCodeEmitter(FunctionPassManager &PM, bool Fast,
- bool DumpAsm, MachineCodeEmitter &MCE);
- virtual const bool getEnableTailMergeDefault() const;
+ TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
+
+ /// \brief Register PPC analysis passes with a pass manager.
+ void addAnalysisPasses(PassManagerBase &PM) override;
};
/// PPC32TargetMachine - PowerPC 32-bit target machine.
///
class PPC32TargetMachine : public PPCTargetMachine {
+ virtual void anchor();
public:
- PPC32TargetMachine(const Module &M, const std::string &FS);
-
- static unsigned getJITMatchQuality();
- static unsigned getModuleMatchQuality(const Module &M);
+ PPC32TargetMachine(const Target &T, StringRef TT,
+ StringRef CPU, StringRef FS, const TargetOptions &Options,
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
};
/// PPC64TargetMachine - PowerPC 64-bit target machine.
///
class PPC64TargetMachine : public PPCTargetMachine {
+ virtual void anchor();
public:
- PPC64TargetMachine(const Module &M, const std::string &FS);
-
- static unsigned getJITMatchQuality();
- static unsigned getModuleMatchQuality(const Module &M);
+ PPC64TargetMachine(const Target &T, StringRef TT,
+ StringRef CPU, StringRef FS, const TargetOptions &Options,
+ Reloc::Model RM, CodeModel::Model CM,
+ CodeGenOpt::Level OL);
};
} // end namespace llvm