//
//===----------------------------------------------------------------------===//
+#define DEBUG_TYPE "isel"
#include "PowerPC.h"
#include "PowerPCInstrBuilder.h"
#include "PowerPCInstrInfo.h"
#include "llvm/DerivedTypes.h"
#include "llvm/Function.h"
#include "llvm/Instructions.h"
-#include "llvm/IntrinsicLowering.h"
#include "llvm/Pass.h"
+#include "llvm/CodeGen/IntrinsicLowering.h"
#include "llvm/CodeGen/MachineConstantPool.h"
#include "llvm/CodeGen/MachineFrameInfo.h"
#include "llvm/CodeGen/MachineFunction.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Support/GetElementPtrTypeIterator.h"
#include "llvm/Support/InstVisitor.h"
+#include "Support/Debug.h"
+#include <vector>
+#include <iostream>
using namespace llvm;
namespace {
- /// TypeClass - Used by the PowerPC backend to group LLVM types by their basic PPC
- /// Representation.
+ /// TypeClass - Used by the PowerPC backend to group LLVM types by their basic
+ /// PPC Representation.
///
enum TypeClass {
- cByte, cShort, cInt, cFP, cLong
+ cByte, cShort, cInt, cFP32, cFP64, cLong
};
}
/// size of the type, and whether or not it is floating point.
///
static inline TypeClass getClass(const Type *Ty) {
- switch (Ty->getPrimitiveID()) {
+ switch (Ty->getTypeID()) {
case Type::SByteTyID:
case Type::UByteTyID: return cByte; // Byte operands are class #0
case Type::ShortTyID:
case Type::UShortTyID: return cShort; // Short operands are class #1
case Type::IntTyID:
case Type::UIntTyID:
- case Type::PointerTyID: return cInt; // Int's and pointers are class #2
+ case Type::PointerTyID: return cInt; // Ints and pointers are class #2
- case Type::FloatTyID:
- case Type::DoubleTyID: return cFP; // Floating Point is #3
+ case Type::FloatTyID: return cFP32; // Single float is #3
+ case Type::DoubleTyID: return cFP64; // Double Point is #4
case Type::LongTyID:
- case Type::ULongTyID: return cLong; // Longs are class #4
+ case Type::ULongTyID: return cLong; // Longs are class #5
default:
assert(0 && "Invalid type to getClass!");
return cByte; // not reached
MachineFunction *F; // The function we are compiling into
MachineBasicBlock *BB; // The current MBB we are compiling
int VarArgsFrameIndex; // FrameIndex for start of varargs area
- int ReturnAddressIndex; // FrameIndex for the return address
- std::map<Value*, unsigned> RegMap; // Mapping between Val's and SSA Regs
+ std::map<Value*, unsigned> RegMap; // Mapping between Values and SSA Regs
+
+ // External functions used in the Module
+ Function *fmodfFn, *fmodFn, *__moddi3Fn, *__divdi3Fn, *__umoddi3Fn,
+ *__udivdi3Fn, *__fixsfdiFn, *__fixdfdiFn, *__floatdisfFn, *__floatdidfFn,
+ *mallocFn, *freeFn;
// MBBMap - Mapping between LLVM BB -> Machine BB
std::map<const BasicBlock*, MachineBasicBlock*> MBBMap;
ISel(TargetMachine &tm) : TM(tm), F(0), BB(0) {}
+ bool doInitialization(Module &M) {
+ // Add external functions that we may call
+ Type *d = Type::DoubleTy;
+ Type *f = Type::FloatTy;
+ Type *l = Type::LongTy;
+ Type *ul = Type::ULongTy;
+ Type *voidPtr = PointerType::get(Type::SByteTy);
+ // float fmodf(float, float);
+ fmodfFn = M.getOrInsertFunction("fmodf", f, f, f, 0);
+ // double fmod(double, double);
+ fmodFn = M.getOrInsertFunction("fmod", d, d, d, 0);
+ // long __moddi3(long, long);
+ __moddi3Fn = M.getOrInsertFunction("__moddi3", l, l, l, 0);
+ // long __divdi3(long, long);
+ __divdi3Fn = M.getOrInsertFunction("__divdi3", l, l, l, 0);
+ // unsigned long __umoddi3(unsigned long, unsigned long);
+ __umoddi3Fn = M.getOrInsertFunction("__umoddi3", ul, ul, ul, 0);
+ // unsigned long __udivdi3(unsigned long, unsigned long);
+ __udivdi3Fn = M.getOrInsertFunction("__udivdi3", ul, ul, ul, 0);
+ // long __fixsfdi(float)
+ __fixdfdiFn = M.getOrInsertFunction("__fixsfdi", l, f, 0);
+ // long __fixdfdi(double)
+ __fixdfdiFn = M.getOrInsertFunction("__fixdfdi", l, d, 0);
+ // float __floatdisf(long)
+ __floatdisfFn = M.getOrInsertFunction("__floatdisf", f, l, 0);
+ // double __floatdidf(long)
+ __floatdidfFn = M.getOrInsertFunction("__floatdidf", d, l, 0);
+ // void* malloc(size_t)
+ mallocFn = M.getOrInsertFunction("malloc", voidPtr, Type::UIntTy, 0);
+ // void free(void*)
+ freeFn = M.getOrInsertFunction("free", Type::VoidTy, voidPtr, 0);
+ return false;
+ }
+
/// runOnFunction - Top level implementation of instruction selection for
/// the entire function.
///
BB = &F->front();
- // Set up a frame object for the return address. This is used by the
- // llvm.returnaddress & llvm.frameaddress intrinisics.
- ReturnAddressIndex = F->getFrameInfo()->CreateFixedObject(4, -4);
-
// Copy incoming arguments off of the stack...
LoadArgumentsToVirtualRegs(Fn);
ValueRecord(Value *V) : Val(V), Reg(0), Ty(V->getType()) {}
};
void doCall(const ValueRecord &Ret, MachineInstr *CallMI,
- const std::vector<ValueRecord> &Args);
+ const std::vector<ValueRecord> &Args, bool isVarArg);
void visitCallInst(CallInst &I);
void visitIntrinsicCall(Intrinsic::ID ID, CallInst &I);
///
unsigned ISel::getReg(Value *V, MachineBasicBlock *MBB,
MachineBasicBlock::iterator IPt) {
- // If this operand is a constant, emit the code to copy the constant into
- // the register here...
- //
if (Constant *C = dyn_cast<Constant>(V)) {
unsigned Reg = makeAnotherReg(V->getType());
copyConstantToRegister(MBB, IPt, C, Reg);
return Reg;
- } else if (GlobalValue *GV = dyn_cast<GlobalValue>(V)) {
- unsigned Reg1 = makeAnotherReg(V->getType());
- unsigned Reg2 = makeAnotherReg(V->getType());
- // Move the address of the global into the register
- BuildMI(*MBB, IPt, PPC32::LOADHiAddr, 2, Reg1).addReg(PPC32::R0).addGlobalAddress(GV);
- BuildMI(*MBB, IPt, PPC32::LOADLoAddr, 2, Reg2).addReg(Reg1).addGlobalAddress(GV);
- return Reg2;
} else if (CastInst *CI = dyn_cast<CastInst>(V)) {
// Do not emit noop casts at all.
if (getClassB(CI->getType()) == getClassB(CI->getOperand(0)->getType()))
void ISel::copyConstantToRegister(MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
Constant *C, unsigned R) {
- if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) {
- unsigned Class = 0;
- switch (CE->getOpcode()) {
- case Instruction::GetElementPtr:
- emitGEPOperation(MBB, IP, CE->getOperand(0),
- CE->op_begin()+1, CE->op_end(), R);
- return;
- case Instruction::Cast:
- emitCastOperation(MBB, IP, CE->getOperand(0), CE->getType(), R);
- return;
-
- case Instruction::Xor: ++Class; // FALL THROUGH
- case Instruction::Or: ++Class; // FALL THROUGH
- case Instruction::And: ++Class; // FALL THROUGH
- case Instruction::Sub: ++Class; // FALL THROUGH
- case Instruction::Add:
- emitSimpleBinaryOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
- Class, R);
- return;
-
- case Instruction::Mul:
- emitMultiply(MBB, IP, CE->getOperand(0), CE->getOperand(1), R);
- return;
-
- case Instruction::Div:
- case Instruction::Rem:
- emitDivRemOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
- CE->getOpcode() == Instruction::Div, R);
- return;
-
- case Instruction::SetNE:
- case Instruction::SetEQ:
- case Instruction::SetLT:
- case Instruction::SetGT:
- case Instruction::SetLE:
- case Instruction::SetGE:
- emitSetCCOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
- CE->getOpcode(), R);
- return;
-
- case Instruction::Shl:
- case Instruction::Shr:
- emitShiftOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
- CE->getOpcode() == Instruction::Shl, CE->getType(), R);
- return;
-
- case Instruction::Select:
- emitSelectOperation(MBB, IP, CE->getOperand(0), CE->getOperand(1),
- CE->getOperand(2), R);
- return;
-
- default:
- std::cerr << "Offending expr: " << C << "\n";
- assert(0 && "Constant expression not yet handled!\n");
- }
- }
-
if (C->getType()->isIntegral()) {
unsigned Class = getClassB(C->getType());
if (Class == cLong) {
// Copy the value into the register pair.
uint64_t Val = cast<ConstantInt>(C)->getRawValue();
- unsigned hiTmp = makeAnotherReg(Type::IntTy);
- unsigned loTmp = makeAnotherReg(Type::IntTy);
- BuildMI(*MBB, IP, PPC32::ADDIS, 2, loTmp).addReg(PPC32::R0).addImm(Val >> 48);
- BuildMI(*MBB, IP, PPC32::ORI, 2, R).addReg(loTmp).addImm((Val >> 32) & 0xFFFF);
- BuildMI(*MBB, IP, PPC32::ADDIS, 2, hiTmp).addReg(PPC32::R0).addImm((Val >> 16) & 0xFFFF);
- BuildMI(*MBB, IP, PPC32::ORI, 2, R+1).addReg(hiTmp).addImm(Val & 0xFFFF);
+
+ if (Val < (1ULL << 16)) {
+ BuildMI(*MBB, IP, PPC32::LI, 1, R).addImm(Val & 0xFFFF);
+ BuildMI(*MBB, IP, PPC32::LI, 1, R+1).addImm(0);
+ } else if (Val < (1ULL << 32)) {
+ unsigned Temp = makeAnotherReg(Type::IntTy);
+ BuildMI(*MBB, IP, PPC32::LIS, 1, Temp).addImm((Val >> 16) & 0xFFFF);
+ BuildMI(*MBB, IP, PPC32::ORI, 2, R).addReg(Temp).addImm(Val & 0xFFFF);
+ BuildMI(*MBB, IP, PPC32::LI, 1, R+1).addImm(0);
+ } else if (Val < (1ULL << 48)) {
+ unsigned Temp = makeAnotherReg(Type::IntTy);
+ BuildMI(*MBB, IP, PPC32::LIS, 1, Temp).addImm((Val >> 16) & 0xFFFF);
+ BuildMI(*MBB, IP, PPC32::ORI, 2, R).addReg(Temp).addImm(Val & 0xFFFF);
+ BuildMI(*MBB, IP, PPC32::LI, 1, R+1).addImm((Val >> 32) & 0xFFFF);
+ } else {
+ unsigned TempLo = makeAnotherReg(Type::IntTy);
+ unsigned TempHi = makeAnotherReg(Type::IntTy);
+ BuildMI(*MBB, IP, PPC32::LIS, 1, TempLo).addImm((Val >> 16) & 0xFFFF);
+ BuildMI(*MBB, IP, PPC32::ORI, 2, R).addReg(TempLo).addImm(Val & 0xFFFF);
+ BuildMI(*MBB, IP, PPC32::LIS, 1, TempHi).addImm((Val >> 48) & 0xFFFF);
+ BuildMI(*MBB, IP, PPC32::ORI, 2, R+1).addReg(TempHi)
+ .addImm((Val >> 32) & 0xFFFF);
+ }
return;
}
assert(Class <= cInt && "Type not handled yet!");
if (C->getType() == Type::BoolTy) {
- BuildMI(*MBB, IP, PPC32::ADDI, 2, R).addReg(PPC32::R0).addImm(C == ConstantBool::True);
+ BuildMI(*MBB, IP, PPC32::LI, 1, R).addImm(C == ConstantBool::True);
} else if (Class == cByte || Class == cShort) {
ConstantInt *CI = cast<ConstantInt>(C);
- BuildMI(*MBB, IP, PPC32::ADDI, 2, R).addReg(PPC32::R0).addImm(CI->getRawValue());
+ BuildMI(*MBB, IP, PPC32::LI, 1, R).addImm(CI->getRawValue());
} else {
ConstantInt *CI = cast<ConstantInt>(C);
int TheVal = CI->getRawValue() & 0xFFFFFFFF;
if (TheVal < 32768 && TheVal >= -32768) {
- BuildMI(*MBB, IP, PPC32::ADDI, 2, R).addReg(PPC32::R0).addImm(CI->getRawValue());
- } else {
- unsigned TmpReg = makeAnotherReg(Type::IntTy);
- BuildMI(*MBB, IP, PPC32::ADDIS, 2, TmpReg).addReg(PPC32::R0).addImm(CI->getRawValue() >> 16);
- BuildMI(*MBB, IP, PPC32::ORI, 2, R).addReg(TmpReg).addImm(CI->getRawValue() & 0xFFFF);
- }
+ BuildMI(*MBB, IP, PPC32::LI, 1, R).addImm(CI->getRawValue());
+ } else {
+ unsigned TmpReg = makeAnotherReg(Type::IntTy);
+ BuildMI(*MBB, IP, PPC32::LIS, 1, TmpReg)
+ .addImm(CI->getRawValue() >> 16);
+ BuildMI(*MBB, IP, PPC32::ORI, 2, R).addReg(TmpReg)
+ .addImm(CI->getRawValue() & 0xFFFF);
+ }
}
} else if (ConstantFP *CFP = dyn_cast<ConstantFP>(C)) {
- // We need to spill the constant to memory...
- MachineConstantPool *CP = F->getConstantPool();
- unsigned CPI = CP->getConstantPoolIndex(CFP);
- const Type *Ty = CFP->getType();
-
- assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
- unsigned LoadOpcode = Ty == Type::FloatTy ? PPC32::LFS : PPC32::LFD;
- addConstantPoolReference(BuildMI(*MBB, IP, LoadOpcode, 2, R), CPI);
+ // We need to spill the constant to memory...
+ MachineConstantPool *CP = F->getConstantPool();
+ unsigned CPI = CP->getConstantPoolIndex(CFP);
+ const Type *Ty = CFP->getType();
+
+ assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
+
+ // Load addr of constant to reg; constant is located at PC + distance
+ unsigned CurPC = makeAnotherReg(Type::IntTy);
+ unsigned Reg1 = makeAnotherReg(Type::IntTy);
+ unsigned Reg2 = makeAnotherReg(Type::IntTy);
+ // Move PC to destination reg
+ BuildMI(*MBB, IP, PPC32::MovePCtoLR, 0, CurPC);
+ // Move value at PC + distance into return reg
+ BuildMI(*MBB, IP, PPC32::LOADHiAddr, 2, Reg1).addReg(CurPC)
+ .addConstantPoolIndex(CPI);
+ BuildMI(*MBB, IP, PPC32::LOADLoDirect, 2, Reg2).addReg(Reg1)
+ .addConstantPoolIndex(CPI);
+
+ unsigned LoadOpcode = (Ty == Type::FloatTy) ? PPC32::LFS : PPC32::LFD;
+ BuildMI(*MBB, IP, LoadOpcode, 2, R).addImm(0).addReg(Reg2);
} else if (isa<ConstantPointerNull>(C)) {
// Copy zero (null pointer) to the register.
- BuildMI(*MBB, IP, PPC32::ADDI, 2, R).addReg(PPC32::R0).addImm(0);
- } else if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(C)) {
- BuildMI(*MBB, IP, PPC32::ADDIS, 2, R).addReg(PPC32::R0).addGlobalAddress(CPR->getValue());
- BuildMI(*MBB, IP, PPC32::ORI, 2, R).addReg(PPC32::R0).addGlobalAddress(CPR->getValue());
+ BuildMI(*MBB, IP, PPC32::LI, 1, R).addImm(0);
+ } else if (GlobalValue *GV = dyn_cast<GlobalValue>(C)) {
+ // GV is located at PC + distance
+ unsigned CurPC = makeAnotherReg(Type::IntTy);
+ unsigned TmpReg = makeAnotherReg(GV->getType());
+ unsigned Opcode = GV->hasWeakLinkage() ?
+ PPC32::LOADLoIndirect :
+ PPC32::LOADLoDirect;
+
+ // Move PC to destination reg
+ BuildMI(*MBB, IP, PPC32::MovePCtoLR, 0, CurPC);
+ // Move value at PC + distance into return reg
+ BuildMI(*MBB, IP, PPC32::LOADHiAddr, 2, TmpReg).addReg(CurPC)
+ .addGlobalAddress(GV);
+ BuildMI(*MBB, IP, Opcode, 2, R).addReg(TmpReg).addGlobalAddress(GV);
} else {
- std::cerr << "Offending constant: " << C << "\n";
+ std::cerr << "Offending constant: " << *C << "\n";
assert(0 && "Type not handled yet!");
}
}
/// FIXME: When we can calculate which args are coming in via registers
/// source them from there instead.
void ISel::LoadArgumentsToVirtualRegs(Function &Fn) {
- unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
+ unsigned ArgOffset = 20; // FIXME why is this not 24?
unsigned GPR_remaining = 8;
unsigned FPR_remaining = 13;
- unsigned GPR_idx = 3;
- unsigned FPR_idx = 1;
-
+ unsigned GPR_idx = 0, FPR_idx = 0;
+ static const unsigned GPR[] = {
+ PPC32::R3, PPC32::R4, PPC32::R5, PPC32::R6,
+ PPC32::R7, PPC32::R8, PPC32::R9, PPC32::R10,
+ };
+ static const unsigned FPR[] = {
+ PPC32::F1, PPC32::F2, PPC32::F3, PPC32::F4, PPC32::F5, PPC32::F6, PPC32::F7,
+ PPC32::F8, PPC32::F9, PPC32::F10, PPC32::F11, PPC32::F12, PPC32::F13
+ };
+
MachineFrameInfo *MFI = F->getFrameInfo();
-
+
for (Function::aiterator I = Fn.abegin(), E = Fn.aend(); I != E; ++I) {
bool ArgLive = !I->use_empty();
unsigned Reg = ArgLive ? getReg(*I) : 0;
switch (getClassB(I->getType())) {
case cByte:
if (ArgLive) {
- FI = MFI->CreateFixedObject(1, ArgOffset);
- if (GPR_remaining > 0) {
- BuildMI(BB, PPC32::OR, 2, Reg).addReg(PPC32::R0+GPR_idx).addReg(PPC32::R0+GPR_idx);
- } else {
- addFrameReference(BuildMI(BB, PPC32::LBZ, 2, Reg), FI);
- }
- }
+ FI = MFI->CreateFixedObject(4, ArgOffset);
+ if (GPR_remaining > 0) {
+ BuildMI(BB, PPC32::IMPLICIT_DEF, 0, GPR[GPR_idx]);
+ BuildMI(BB, PPC32::OR, 2, Reg).addReg(GPR[GPR_idx])
+ .addReg(GPR[GPR_idx]);
+ } else {
+ addFrameReference(BuildMI(BB, PPC32::LBZ, 2, Reg), FI);
+ }
+ }
break;
case cShort:
if (ArgLive) {
- FI = MFI->CreateFixedObject(2, ArgOffset);
- if (GPR_remaining > 0) {
- BuildMI(BB, PPC32::OR, 2, Reg).addReg(PPC32::R0+GPR_idx).addReg(PPC32::R0+GPR_idx);
- } else {
- addFrameReference(BuildMI(BB, PPC32::LHZ, 2, Reg), FI);
- }
- }
+ FI = MFI->CreateFixedObject(4, ArgOffset);
+ if (GPR_remaining > 0) {
+ BuildMI(BB, PPC32::IMPLICIT_DEF, 0, GPR[GPR_idx]);
+ BuildMI(BB, PPC32::OR, 2, Reg).addReg(GPR[GPR_idx])
+ .addReg(GPR[GPR_idx]);
+ } else {
+ addFrameReference(BuildMI(BB, PPC32::LHZ, 2, Reg), FI);
+ }
+ }
break;
case cInt:
if (ArgLive) {
FI = MFI->CreateFixedObject(4, ArgOffset);
- if (GPR_remaining > 0) {
- BuildMI(BB, PPC32::OR, 2, Reg).addReg(PPC32::R0+GPR_idx).addReg(PPC32::R0+GPR_idx);
- } else {
- addFrameReference(BuildMI(BB, PPC32::LWZ, 2, Reg), FI);
- }
- }
+ if (GPR_remaining > 0) {
+ BuildMI(BB, PPC32::IMPLICIT_DEF, 0, GPR[GPR_idx]);
+ BuildMI(BB, PPC32::OR, 2, Reg).addReg(GPR[GPR_idx])
+ .addReg(GPR[GPR_idx]);
+ } else {
+ addFrameReference(BuildMI(BB, PPC32::LWZ, 2, Reg), FI);
+ }
+ }
break;
case cLong:
if (ArgLive) {
FI = MFI->CreateFixedObject(8, ArgOffset);
- if (GPR_remaining > 1) {
- BuildMI(BB, PPC32::OR, 2, Reg).addReg(PPC32::R0+GPR_idx).addReg(PPC32::R0+GPR_idx);
- BuildMI(BB, PPC32::OR, 2, Reg+1).addReg(PPC32::R0+GPR_idx+1).addReg(PPC32::R0+GPR_idx+1);
- } else {
- addFrameReference(BuildMI(BB, PPC32::LWZ, 2, Reg), FI);
- addFrameReference(BuildMI(BB, PPC32::LWZ, 2, Reg+1), FI, 4);
- }
- }
+ if (GPR_remaining > 1) {
+ BuildMI(BB, PPC32::IMPLICIT_DEF, 0, GPR[GPR_idx]);
+ BuildMI(BB, PPC32::IMPLICIT_DEF, 0, GPR[GPR_idx+1]);
+ BuildMI(BB, PPC32::OR, 2, Reg).addReg(GPR[GPR_idx])
+ .addReg(GPR[GPR_idx]);
+ BuildMI(BB, PPC32::OR, 2, Reg+1).addReg(GPR[GPR_idx+1])
+ .addReg(GPR[GPR_idx+1]);
+ } else {
+ addFrameReference(BuildMI(BB, PPC32::LWZ, 2, Reg), FI);
+ addFrameReference(BuildMI(BB, PPC32::LWZ, 2, Reg+1), FI, 4);
+ }
+ }
ArgOffset += 4; // longs require 4 additional bytes
- if (GPR_remaining > 1) {
- GPR_remaining--; // uses up 2 GPRs
- GPR_idx++;
- }
+ if (GPR_remaining > 1) {
+ GPR_remaining--; // uses up 2 GPRs
+ GPR_idx++;
+ }
break;
- case cFP:
+ case cFP32:
+ if (ArgLive) {
+ FI = MFI->CreateFixedObject(4, ArgOffset);
+
+ if (FPR_remaining > 0) {
+ BuildMI(BB, PPC32::IMPLICIT_DEF, 0, FPR[FPR_idx]);
+ BuildMI(BB, PPC32::FMR, 1, Reg).addReg(FPR[FPR_idx]);
+ FPR_remaining--;
+ FPR_idx++;
+ } else {
+ addFrameReference(BuildMI(BB, PPC32::LFS, 2, Reg), FI);
+ }
+ }
+ break;
+ case cFP64:
if (ArgLive) {
- unsigned Opcode;
- if (I->getType() == Type::FloatTy) {
- Opcode = PPC32::LFS;
- FI = MFI->CreateFixedObject(4, ArgOffset);
+ FI = MFI->CreateFixedObject(8, ArgOffset);
+
+ if (FPR_remaining > 0) {
+ BuildMI(BB, PPC32::IMPLICIT_DEF, 0, FPR[FPR_idx]);
+ BuildMI(BB, PPC32::FMR, 1, Reg).addReg(FPR[FPR_idx]);
+ FPR_remaining--;
+ FPR_idx++;
} else {
- Opcode = PPC32::LFD;
- FI = MFI->CreateFixedObject(8, ArgOffset);
+ addFrameReference(BuildMI(BB, PPC32::LFD, 2, Reg), FI);
}
- if (FPR_remaining > 0) {
- BuildMI(BB, PPC32::FMR, 1, Reg).addReg(PPC32::F0+FPR_idx);
- FPR_remaining--;
- FPR_idx++;
- } else {
- addFrameReference(BuildMI(BB, Opcode, 2, Reg), FI);
- }
- }
- if (I->getType() == Type::DoubleTy) {
- ArgOffset += 4; // doubles require 4 additional bytes
- if (GPR_remaining > 0) {
- GPR_remaining--; // uses up 2 GPRs
- GPR_idx++;
- }
- }
+ }
+
+ // doubles require 4 additional bytes and use 2 GPRs of param space
+ ArgOffset += 4;
+ if (GPR_remaining > 0) {
+ GPR_remaining--;
+ GPR_idx++;
+ }
break;
default:
assert(0 && "Unhandled argument type!");
}
ArgOffset += 4; // Each argument takes at least 4 bytes on the stack...
- if (GPR_remaining > 0) {
- GPR_remaining--; // uses up 2 GPRs
- GPR_idx++;
- }
+ if (GPR_remaining > 0) {
+ GPR_remaining--; // uses up 2 GPRs
+ GPR_idx++;
+ }
}
// If the function takes variable number of arguments, add a frame offset for
std::map<MachineBasicBlock*, unsigned> PHIValues;
for (unsigned i = 0, e = PN->getNumIncomingValues(); i != e; ++i) {
- MachineBasicBlock *PredMBB = MBBMap[PN->getIncomingBlock(i)];
+ MachineBasicBlock *PredMBB = 0;
+ for (MachineBasicBlock::pred_iterator PI = MBB.pred_begin (),
+ PE = MBB.pred_end (); PI != PE; ++PI)
+ if (PN->getIncomingBlock(i) == (*PI)->getBasicBlock()) {
+ PredMBB = *PI;
+ break;
+ }
+ assert (PredMBB && "Couldn't find incoming machine-cfg edge for phi");
+
unsigned ValReg;
std::map<MachineBasicBlock*, unsigned>::iterator EntryIt =
PHIValues.lower_bound(PredMBB);
if (SCI->hasOneUse()) {
Instruction *User = cast<Instruction>(SCI->use_back());
if ((isa<BranchInst>(User) || isa<SelectInst>(User)) &&
- SCI->getParent() == User->getParent() &&
- (getClassB(SCI->getOperand(0)->getType()) != cLong ||
- SCI->getOpcode() == Instruction::SetEQ ||
- SCI->getOpcode() == Instruction::SetNE))
+ SCI->getParent() == User->getParent())
return SCI;
}
return 0;
// order of the opcodes.
//
static unsigned getSetCCNumber(unsigned Opcode) {
- switch(Opcode) {
+ switch (Opcode) {
default: assert(0 && "Unknown setcc instruction!");
case Instruction::SetEQ: return 0;
case Instruction::SetNE: return 1;
}
}
+static unsigned getPPCOpcodeForSetCCNumber(unsigned Opcode) {
+ switch (Opcode) {
+ default: assert(0 && "Unknown setcc instruction!");
+ case Instruction::SetEQ: return PPC32::BEQ;
+ case Instruction::SetNE: return PPC32::BNE;
+ case Instruction::SetLT: return PPC32::BLT;
+ case Instruction::SetGE: return PPC32::BGE;
+ case Instruction::SetGT: return PPC32::BGT;
+ case Instruction::SetLE: return PPC32::BLE;
+ }
+}
+
+static unsigned invertPPCBranchOpcode(unsigned Opcode) {
+ switch (Opcode) {
+ default: assert(0 && "Unknown PPC32 branch opcode!");
+ case PPC32::BEQ: return PPC32::BNE;
+ case PPC32::BNE: return PPC32::BEQ;
+ case PPC32::BLT: return PPC32::BGE;
+ case PPC32::BGE: return PPC32::BLT;
+ case PPC32::BGT: return PPC32::BLE;
+ case PPC32::BLE: return PPC32::BGT;
+ }
+}
+
/// emitUCOM - emits an unordered FP compare.
void ISel::emitUCOM(MachineBasicBlock *MBB, MachineBasicBlock::iterator IP,
unsigned LHS, unsigned RHS) {
- BuildMI(*MBB, IP, PPC32::FCMPU, 2, PPC32::CR0).addReg(LHS).addReg(RHS);
+ BuildMI(*MBB, IP, PPC32::FCMPU, 2, PPC32::CR0).addReg(LHS).addReg(RHS);
}
-// EmitComparison - This function emits a comparison of the two operands,
-// returning the extended setcc code to use.
+/// EmitComparison - emits a comparison of the two operands, returning the
+/// extended setcc code to use. The result is in CR0.
+///
unsigned ISel::EmitComparison(unsigned OpNum, Value *Op0, Value *Op1,
MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP) {
// Special case handling of: cmp R, i
if (isa<ConstantPointerNull>(Op1)) {
- BuildMI(*MBB, IP, PPC32::CMPI, 2, PPC32::CR0).addReg(Op0r).addImm(0);
+ BuildMI(*MBB, IP, PPC32::CMPI, 2, PPC32::CR0).addReg(Op0r).addImm(0);
} else if (ConstantInt *CI = dyn_cast<ConstantInt>(Op1)) {
if (Class == cByte || Class == cShort || Class == cInt) {
unsigned Op1v = CI->getRawValue();
// Mask off any upper bits of the constant, if there are any...
Op1v &= (1ULL << (8 << Class)) - 1;
- // Compare immediate or promote to reg?
- if (Op1v <= 32767) {
- BuildMI(*MBB, IP, CompTy->isSigned() ? PPC32::CMPI : PPC32::CMPLI, 3, PPC32::CR0).addImm(0).addReg(Op0r).addImm(Op1v);
- } else {
- unsigned Op1r = getReg(Op1, MBB, IP);
- BuildMI(*MBB, IP, CompTy->isSigned() ? PPC32::CMP : PPC32::CMPL, 3, PPC32::CR0).addImm(0).addReg(Op0r).addReg(Op1r);
- }
+ // Compare immediate or promote to reg?
+ if (Op1v <= 32767) {
+ BuildMI(*MBB, IP, CompTy->isSigned() ? PPC32::CMPI : PPC32::CMPLI, 3,
+ PPC32::CR0).addImm(0).addReg(Op0r).addImm(Op1v);
+ } else {
+ unsigned Op1r = getReg(Op1, MBB, IP);
+ BuildMI(*MBB, IP, CompTy->isSigned() ? PPC32::CMP : PPC32::CMPL, 3,
+ PPC32::CR0).addImm(0).addReg(Op0r).addReg(Op1r);
+ }
return OpNum;
} else {
assert(Class == cLong && "Unknown integer class!");
if (OpNum < 2) { // seteq, setne
unsigned LoTmp = Op0r;
if (LowCst != 0) {
- unsigned LoLow = makeAnotherReg(Type::IntTy);
+ unsigned LoLow = makeAnotherReg(Type::IntTy);
unsigned LoTmp = makeAnotherReg(Type::IntTy);
BuildMI(*MBB, IP, PPC32::XORI, 2, LoLow).addReg(Op0r).addImm(LowCst);
- BuildMI(*MBB, IP, PPC32::XORIS, 2, LoTmp).addReg(LoLow).addImm(LowCst >> 16);
+ BuildMI(*MBB, IP, PPC32::XORIS, 2, LoTmp).addReg(LoLow)
+ .addImm(LowCst >> 16);
}
unsigned HiTmp = Op0r+1;
if (HiCst != 0) {
- unsigned HiLow = makeAnotherReg(Type::IntTy);
+ unsigned HiLow = makeAnotherReg(Type::IntTy);
unsigned HiTmp = makeAnotherReg(Type::IntTy);
BuildMI(*MBB, IP, PPC32::XORI, 2, HiLow).addReg(Op0r+1).addImm(HiCst);
- BuildMI(*MBB, IP, PPC32::XORIS, 2, HiTmp).addReg(HiLow).addImm(HiCst >> 16);
+ BuildMI(*MBB, IP, PPC32::XORIS, 2, HiTmp).addReg(HiLow)
+ .addImm(HiCst >> 16);
}
unsigned FinalTmp = makeAnotherReg(Type::IntTy);
BuildMI(*MBB, IP, PPC32::ORo, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
- //BuildMI(*MBB, IP, PPC32::CMPLI, 2, PPC32::CR0).addReg(FinalTmp).addImm(0);
return OpNum;
} else {
- // Emit a sequence of code which compares the high and low parts once
- // each, then uses a conditional move to handle the overflow case. For
- // example, a setlt for long would generate code like this:
- //
- // AL = lo(op1) < lo(op2) // Always unsigned comparison
- // BL = hi(op1) < hi(op2) // Signedness depends on operands
- // dest = hi(op1) == hi(op2) ? BL : AL;
- //
-
- // FIXME: Not Yet Implemented
- return OpNum;
+ unsigned ConstReg = makeAnotherReg(CompTy);
+ unsigned CondReg = makeAnotherReg(Type::IntTy);
+ unsigned TmpReg1 = makeAnotherReg(Type::IntTy);
+ unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
+ copyConstantToRegister(MBB, IP, CI, ConstReg);
+
+ // FIXME: this is inefficient, but avoids branches
+
+ // compare hi word -> cr0
+ // compare lo word -> cr1
+ BuildMI(*MBB, IP, CompTy->isSigned() ? PPC32::CMPI : PPC32::CMPLI, 3,
+ PPC32::CR0).addImm(0).addReg(Op0r+1).addReg(ConstReg+1);
+ BuildMI(*MBB, IP, PPC32::CMPLI, 3, PPC32::CR1).addImm(0).addReg(Op0r)
+ .addReg(ConstReg);
+ BuildMI(*MBB, IP, PPC32::MFCR, 0, CondReg);
+ // shift amount = 4 * CR0[EQ]
+ BuildMI(*MBB, IP, PPC32::RLWINM, 4, TmpReg1).addReg(CondReg).addImm(5)
+ .addImm(29).addImm(29);
+ // shift cr1 into cr0 position if op0.hi and const.hi were equal
+ BuildMI(*MBB, IP, PPC32::SLW, 2, TmpReg2).addReg(CondReg)
+ .addReg(TmpReg1);
+ // cr0 == ( op0.hi != const.hi ) ? cr0 : cr1
+ BuildMI(*MBB, IP, PPC32::MTCRF, 2).addImm(1).addReg(TmpReg2);
+
+ return OpNum;
}
}
}
case cByte:
case cShort:
case cInt:
- BuildMI(*MBB, IP, CompTy->isSigned() ? PPC32::CMP : PPC32::CMPL, 2, PPC32::CR0).addReg(Op0r).addReg(Op1r);
+ BuildMI(*MBB, IP, CompTy->isSigned() ? PPC32::CMP : PPC32::CMPL, 2,
+ PPC32::CR0).addReg(Op0r).addReg(Op1r);
break;
- case cFP:
+
+ case cFP32:
+ case cFP64:
emitUCOM(MBB, IP, Op0r, Op1r);
break;
BuildMI(*MBB, IP, PPC32::XOR, 2, LoTmp).addReg(Op0r).addReg(Op1r);
BuildMI(*MBB, IP, PPC32::XOR, 2, HiTmp).addReg(Op0r+1).addReg(Op1r+1);
BuildMI(*MBB, IP, PPC32::ORo, 2, FinalTmp).addReg(LoTmp).addReg(HiTmp);
- //BuildMI(*MBB, IP, PPC32::CMPLI, 2, PPC32::CR0).addReg(FinalTmp).addImm(0);
break; // Allow the sete or setne to be generated from flags set by OR
} else {
- // Emit a sequence of code which compares the high and low parts once
- // each, then uses a conditional move to handle the overflow case. For
- // example, a setlt for long would generate code like this:
- //
- // AL = lo(op1) < lo(op2) // Signedness depends on operands
- // BL = hi(op1) < hi(op2) // Always unsigned comparison
- // dest = hi(op1) == hi(op2) ? BL : AL;
- //
-
- // FIXME: Not Yet Implemented
+ unsigned CondReg = makeAnotherReg(Type::IntTy);
+ unsigned TmpReg1 = makeAnotherReg(Type::IntTy);
+ unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
+
+ // FIXME: this is inefficient, but avoids branches
+
+ // compare hi word -> cr0
+ // compare lo word -> cr1
+ BuildMI(*MBB, IP, CompTy->isSigned() ? PPC32::CMPI : PPC32::CMPLI, 3,
+ PPC32::CR0).addImm(0).addReg(Op0r+1).addReg(Op1r+1);
+ BuildMI(*MBB, IP, PPC32::CMPLI, 3, PPC32::CR1).addImm(0).addReg(Op0r)
+ .addReg(Op1r);
+ BuildMI(*MBB, IP, PPC32::MFCR, 0, CondReg);
+ // shift amount = 4 * CR0[EQ]
+ BuildMI(*MBB, IP, PPC32::RLWINM, 4, TmpReg1).addReg(CondReg).addImm(5)
+ .addImm(29).addImm(29);
+ // shift cr1 into cr0 position if op0.hi and op1.hi were equal
+ BuildMI(*MBB, IP, PPC32::SLW, 2, TmpReg2).addReg(CondReg)
+ .addReg(TmpReg1);
+ // cr0 == ( op0.hi != op1.hi ) ? cr0 : cr1
+ BuildMI(*MBB, IP, PPC32::MTCRF, 2).addImm(1).addReg(TmpReg2);
+
return OpNum;
}
}
return OpNum;
}
-/// SetCC instructions - Here we just emit boilerplate code to set a byte-sized
-/// register, then move it to wherever the result should be.
+/// visitSetCondInst - emit code to calculate the condition via
+/// EmitComparison(), and possibly store a 0 or 1 to a register as a result
///
void ISel::visitSetCondInst(SetCondInst &I) {
if (canFoldSetCCIntoBranchOrSelect(&I))
- return; // Fold this into a branch or select.
+ return;
unsigned DestReg = getReg(I);
- MachineBasicBlock::iterator MII = BB->end();
- emitSetCCOperation(BB, MII, I.getOperand(0), I.getOperand(1), I.getOpcode(),DestReg);
-}
-
-/// emitSetCCOperation - Common code shared between visitSetCondInst and
-/// constant expression support.
-///
-/// FIXME: this is wrong. we should figure out a way to guarantee
-/// TargetReg is a CR and then make it a no-op
-void ISel::emitSetCCOperation(MachineBasicBlock *MBB,
- MachineBasicBlock::iterator IP,
- Value *Op0, Value *Op1, unsigned Opcode,
- unsigned TargetReg) {
- unsigned OpNum = getSetCCNumber(Opcode);
- OpNum = EmitComparison(OpNum, Op0, Op1, MBB, IP);
-
- // The value is already in CR0 at this point, do nothing.
+ unsigned OpNum = I.getOpcode();
+ const Type *Ty = I.getOperand (0)->getType();
+
+ EmitComparison(OpNum, I.getOperand(0), I.getOperand(1), BB, BB->end());
+
+ unsigned Opcode = getPPCOpcodeForSetCCNumber(OpNum);
+ MachineBasicBlock *thisMBB = BB;
+ const BasicBlock *LLVM_BB = BB->getBasicBlock();
+ ilist<MachineBasicBlock>::iterator It = BB;
+ ++It;
+
+ // thisMBB:
+ // ...
+ // cmpTY cr0, r1, r2
+ // bCC copy1MBB
+ // b copy0MBB
+
+ // FIXME: we wouldn't need copy0MBB (we could fold it into thisMBB)
+ // if we could insert other, non-terminator instructions after the
+ // bCC. But MBB->getFirstTerminator() can't understand this.
+ MachineBasicBlock *copy1MBB = new MachineBasicBlock(LLVM_BB);
+ F->getBasicBlockList().insert(It, copy1MBB);
+ BuildMI(BB, Opcode, 2).addReg(PPC32::CR0).addMBB(copy1MBB);
+ MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
+ F->getBasicBlockList().insert(It, copy0MBB);
+ BuildMI(BB, PPC32::B, 1).addMBB(copy0MBB);
+ // Update machine-CFG edges
+ BB->addSuccessor(copy1MBB);
+ BB->addSuccessor(copy0MBB);
+
+ // copy0MBB:
+ // %FalseValue = li 0
+ // b sinkMBB
+ BB = copy0MBB;
+ unsigned FalseValue = makeAnotherReg(I.getType());
+ BuildMI(BB, PPC32::LI, 1, FalseValue).addImm(0);
+ MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
+ F->getBasicBlockList().insert(It, sinkMBB);
+ BuildMI(BB, PPC32::B, 1).addMBB(sinkMBB);
+ // Update machine-CFG edges
+ BB->addSuccessor(sinkMBB);
+
+ DEBUG(std::cerr << "thisMBB is at " << (void*)thisMBB << "\n");
+ DEBUG(std::cerr << "copy1MBB is at " << (void*)copy1MBB << "\n");
+ DEBUG(std::cerr << "copy0MBB is at " << (void*)copy0MBB << "\n");
+ DEBUG(std::cerr << "sinkMBB is at " << (void*)sinkMBB << "\n");
+
+ // copy1MBB:
+ // %TrueValue = li 1
+ // b sinkMBB
+ BB = copy1MBB;
+ unsigned TrueValue = makeAnotherReg (I.getType ());
+ BuildMI(BB, PPC32::LI, 1, TrueValue).addImm(1);
+ BuildMI(BB, PPC32::B, 1).addMBB(sinkMBB);
+ // Update machine-CFG edges
+ BB->addSuccessor(sinkMBB);
+
+ // sinkMBB:
+ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
+ // ...
+ BB = sinkMBB;
+ BuildMI(BB, PPC32::PHI, 4, DestReg).addReg(FalseValue)
+ .addMBB(copy0MBB).addReg(TrueValue).addMBB(copy1MBB);
}
-
void ISel::visitSelectInst(SelectInst &SI) {
unsigned DestReg = getReg(SI);
MachineBasicBlock::iterator MII = BB->end();
- emitSelectOperation(BB, MII, SI.getCondition(), SI.getTrueValue(),SI.getFalseValue(), DestReg);
+ emitSelectOperation(BB, MII, SI.getCondition(), SI.getTrueValue(),
+ SI.getFalseValue(), DestReg);
}
/// emitSelect - Common code shared between visitSelectInst and the constant
Value *Cond, Value *TrueVal, Value *FalseVal,
unsigned DestReg) {
unsigned SelectClass = getClassB(TrueVal->getType());
+ unsigned Opcode;
- unsigned TrueReg = getReg(TrueVal, MBB, IP);
- unsigned FalseReg = getReg(FalseVal, MBB, IP);
-
- if (TrueReg == FalseReg) {
- if (SelectClass == cFP) {
- BuildMI(*MBB, IP, PPC32::FMR, 1, DestReg).addReg(TrueReg);
- } else {
- BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(TrueReg).addReg(TrueReg);
- }
-
- if (SelectClass == cLong)
- BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(TrueReg+1).addReg(TrueReg+1);
- return;
- }
+ // See if we can fold the setcc into the select instruction, or if we have
+ // to get the register of the Cond value
+ if (SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(Cond)) {
+ // We successfully folded the setcc into the select instruction.
+
+ unsigned OpNum = getSetCCNumber(SCI->getOpcode());
+ OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), MBB,
+ IP);
+ Opcode = getPPCOpcodeForSetCCNumber(SCI->getOpcode());
+ } else {
+ unsigned CondReg = getReg(Cond, MBB, IP);
- unsigned CondReg = getReg(Cond, MBB, IP);
- unsigned numZeros = makeAnotherReg(Type::IntTy);
- unsigned falseHi = makeAnotherReg(Type::IntTy);
- unsigned falseAll = makeAnotherReg(Type::IntTy);
- unsigned trueAll = makeAnotherReg(Type::IntTy);
- unsigned Temp1 = makeAnotherReg(Type::IntTy);
- unsigned Temp2 = makeAnotherReg(Type::IntTy);
-
- BuildMI(*MBB, IP, PPC32::CNTLZW, 1, numZeros).addReg(CondReg);
- BuildMI(*MBB, IP, PPC32::RLWINM, 4, falseHi).addReg(numZeros).addImm(26).addImm(0).addImm(0);
- BuildMI(*MBB, IP, PPC32::SRAWI, 2, falseAll).addReg(falseHi).addImm(31);
- BuildMI(*MBB, IP, PPC32::NOR, 2, trueAll).addReg(falseAll).addReg(falseAll);
- BuildMI(*MBB, IP, PPC32::AND, 2, Temp1).addReg(TrueReg).addReg(trueAll);
- BuildMI(*MBB, IP, PPC32::AND, 2, Temp2).addReg(FalseReg).addReg(falseAll);
- BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(Temp1).addReg(Temp2);
-
- if (SelectClass == cLong) {
- unsigned Temp3 = makeAnotherReg(Type::IntTy);
- unsigned Temp4 = makeAnotherReg(Type::IntTy);
- BuildMI(*MBB, IP, PPC32::AND, 2, Temp3).addReg(TrueReg+1).addReg(trueAll);
- BuildMI(*MBB, IP, PPC32::AND, 2, Temp4).addReg(FalseReg+1).addReg(falseAll);
- BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(Temp3).addReg(Temp4);
+ BuildMI(*MBB, IP, PPC32::CMPI, 2, PPC32::CR0).addReg(CondReg).addImm(0);
+ Opcode = getPPCOpcodeForSetCCNumber(Instruction::SetNE);
}
-
+
+ // thisMBB:
+ // ...
+ // cmpTY cr0, r1, r2
+ // bCC copy1MBB
+ // b copy0MBB
+
+ MachineBasicBlock *thisMBB = BB;
+ const BasicBlock *LLVM_BB = BB->getBasicBlock();
+ ilist<MachineBasicBlock>::iterator It = BB;
+ ++It;
+
+ // FIXME: we wouldn't need copy0MBB (we could fold it into thisMBB)
+ // if we could insert other, non-terminator instructions after the
+ // bCC. But MBB->getFirstTerminator() can't understand this.
+ MachineBasicBlock *copy1MBB = new MachineBasicBlock(LLVM_BB);
+ F->getBasicBlockList().insert(It, copy1MBB);
+ BuildMI(BB, Opcode, 2).addReg(PPC32::CR0).addMBB(copy1MBB);
+ MachineBasicBlock *copy0MBB = new MachineBasicBlock(LLVM_BB);
+ F->getBasicBlockList().insert(It, copy0MBB);
+ BuildMI(BB, PPC32::B, 1).addMBB(copy0MBB);
+ // Update machine-CFG edges
+ BB->addSuccessor(copy1MBB);
+ BB->addSuccessor(copy0MBB);
+
+ // FIXME: spill code is being generated after the branch and before copy1MBB
+ // this is bad, since it will never be run
+
+ // copy0MBB:
+ // %FalseValue = ...
+ // b sinkMBB
+ BB = copy0MBB;
+ unsigned FalseValue = getReg(FalseVal, BB, BB->begin());
+ MachineBasicBlock *sinkMBB = new MachineBasicBlock(LLVM_BB);
+ F->getBasicBlockList().insert(It, sinkMBB);
+ BuildMI(BB, PPC32::B, 1).addMBB(sinkMBB);
+ // Update machine-CFG edges
+ BB->addSuccessor(sinkMBB);
+
+ // copy1MBB:
+ // %TrueValue = ...
+ // b sinkMBB
+ BB = copy1MBB;
+ unsigned TrueValue = getReg(TrueVal, BB, BB->begin());
+ BuildMI(BB, PPC32::B, 1).addMBB(sinkMBB);
+ // Update machine-CFG edges
+ BB->addSuccessor(sinkMBB);
+
+ // sinkMBB:
+ // %Result = phi [ %FalseValue, copy0MBB ], [ %TrueValue, copy1MBB ]
+ // ...
+ BB = sinkMBB;
+ BuildMI(BB, PPC32::PHI, 4, DestReg).addReg(FalseValue)
+ .addMBB(copy0MBB).addReg(TrueValue).addMBB(copy1MBB);
return;
}
Ty = Type::IntTy;
}
- // If this is a simple constant, just emit a load directly to avoid the copy.
+ // If this is a simple constant, just emit a load directly to avoid the copy
if (ConstantInt *CI = dyn_cast<ConstantInt>(Val)) {
int TheVal = CI->getRawValue() & 0xFFFFFFFF;
if (TheVal < 32768 && TheVal >= -32768) {
- BuildMI(BB, PPC32::ADDI, 2, targetReg).addReg(PPC32::R0).addImm(TheVal);
- } else {
- unsigned TmpReg = makeAnotherReg(Type::IntTy);
- BuildMI(BB, PPC32::ADDIS, 2, TmpReg).addReg(PPC32::R0).addImm(TheVal >> 16);
- BuildMI(BB, PPC32::ORI, 2, targetReg).addReg(TmpReg).addImm(TheVal & 0xFFFF);
- }
+ BuildMI(BB, PPC32::LI, 1, targetReg).addImm(TheVal);
+ } else {
+ unsigned TmpReg = makeAnotherReg(Type::IntTy);
+ BuildMI(BB, PPC32::LIS, 1, TmpReg).addImm(TheVal >> 16);
+ BuildMI(BB, PPC32::ORI, 2, targetReg).addReg(TmpReg)
+ .addImm(TheVal & 0xFFFF);
+ }
return;
}
}
case cByte:
// Extend value into target register (8->32)
if (isUnsigned)
- BuildMI(BB, PPC32::RLWINM, 4, targetReg).addReg(Reg).addZImm(0).addZImm(24).addZImm(31);
+ BuildMI(BB, PPC32::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
+ .addZImm(24).addZImm(31);
else
BuildMI(BB, PPC32::EXTSB, 1, targetReg).addReg(Reg);
break;
case cShort:
// Extend value into target register (16->32)
if (isUnsigned)
- BuildMI(BB, PPC32::RLWINM, 4, targetReg).addReg(Reg).addZImm(0).addZImm(16).addZImm(31);
+ BuildMI(BB, PPC32::RLWINM, 4, targetReg).addReg(Reg).addZImm(0)
+ .addZImm(16).addZImm(31);
else
BuildMI(BB, PPC32::EXTSH, 1, targetReg).addReg(Reg);
break;
case cInt:
// Move value into target register (32->32)
- BuildMI(BB, PPC32::ORI, 2, targetReg).addReg(Reg).addReg(Reg);
+ BuildMI(BB, PPC32::OR, 2, targetReg).addReg(Reg).addReg(Reg);
break;
default:
assert(0 && "Unpromotable operand class in promote32");
}
}
-// just emit blr.
+/// visitReturnInst - implemented with BLR
+///
void ISel::visitReturnInst(ReturnInst &I) {
- Value *RetVal = I.getOperand(0);
-
- switch (getClassB(RetVal->getType())) {
- case cByte: // integral return values: extend or move into r3 and return
- case cShort:
- case cInt:
- promote32(PPC32::R3, ValueRecord(RetVal));
- break;
- case cFP: { // Floats & Doubles: Return in f1
- unsigned RetReg = getReg(RetVal);
- BuildMI(BB, PPC32::FMR, 1, PPC32::F1).addReg(RetReg);
- break;
- }
- case cLong: {
- unsigned RetReg = getReg(RetVal);
- BuildMI(BB, PPC32::OR, 2, PPC32::R3).addReg(RetReg).addReg(RetReg);
- BuildMI(BB, PPC32::OR, 2, PPC32::R4).addReg(RetReg+1).addReg(RetReg+1);
- break;
- }
- default:
- visitInstruction(I);
+ // Only do the processing if this is a non-void return
+ if (I.getNumOperands() > 0) {
+ Value *RetVal = I.getOperand(0);
+ switch (getClassB(RetVal->getType())) {
+ case cByte: // integral return values: extend or move into r3 and return
+ case cShort:
+ case cInt:
+ promote32(PPC32::R3, ValueRecord(RetVal));
+ break;
+ case cFP32:
+ case cFP64: { // Floats & Doubles: Return in f1
+ unsigned RetReg = getReg(RetVal);
+ BuildMI(BB, PPC32::FMR, 1, PPC32::F1).addReg(RetReg);
+ break;
+ }
+ case cLong: {
+ unsigned RetReg = getReg(RetVal);
+ BuildMI(BB, PPC32::OR, 2, PPC32::R3).addReg(RetReg).addReg(RetReg);
+ BuildMI(BB, PPC32::OR, 2, PPC32::R4).addReg(RetReg+1).addReg(RetReg+1);
+ break;
+ }
+ default:
+ visitInstruction(I);
+ }
}
BuildMI(BB, PPC32::BLR, 1).addImm(0);
}
/// just make a fall-through (but we don't currently).
///
void ISel::visitBranchInst(BranchInst &BI) {
- // Update machine-CFG edges
- BB->addSuccessor (MBBMap[BI.getSuccessor(0)]);
- if (BI.isConditional())
- BB->addSuccessor (MBBMap[BI.getSuccessor(1)]);
-
- BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
-
- if (!BI.isConditional()) { // Unconditional branch?
- if (BI.getSuccessor(0) != NextBB)
- BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
- return;
- }
-
+ // Update machine-CFG edges
+ BB->addSuccessor (MBBMap[BI.getSuccessor(0)]);
+ if (BI.isConditional())
+ BB->addSuccessor (MBBMap[BI.getSuccessor(1)]);
+
+ BasicBlock *NextBB = getBlockAfter(BI.getParent()); // BB after current one
+
+ if (!BI.isConditional()) { // Unconditional branch?
+ if (BI.getSuccessor(0) != NextBB)
+ BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
+ return;
+ }
+
// See if we can fold the setcc into the branch itself...
SetCondInst *SCI = canFoldSetCCIntoBranchOrSelect(BI.getCondition());
if (SCI == 0) {
// Nope, cannot fold setcc into this branch. Emit a branch on a condition
// computed some other way...
unsigned condReg = getReg(BI.getCondition());
- BuildMI(BB, PPC32::CMPLI, 3, PPC32::CR0).addImm(0).addReg(condReg).addImm(0);
+ BuildMI(BB, PPC32::CMPLI, 3, PPC32::CR1).addImm(0).addReg(condReg)
+ .addImm(0);
if (BI.getSuccessor(1) == NextBB) {
if (BI.getSuccessor(0) != NextBB)
- BuildMI(BB, PPC32::BC, 3).addImm(4).addImm(2).addMBB(MBBMap[BI.getSuccessor(0)]);
+ BuildMI(BB, PPC32::BNE, 2).addReg(PPC32::CR1)
+ .addMBB(MBBMap[BI.getSuccessor(0)]);
} else {
- BuildMI(BB, PPC32::BC, 3).addImm(12).addImm(2).addMBB(MBBMap[BI.getSuccessor(1)]);
+ BuildMI(BB, PPC32::BEQ, 2).addReg(PPC32::CR1)
+ .addMBB(MBBMap[BI.getSuccessor(1)]);
if (BI.getSuccessor(0) != NextBB)
BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(0)]);
return;
}
-
unsigned OpNum = getSetCCNumber(SCI->getOpcode());
+ unsigned Opcode = getPPCOpcodeForSetCCNumber(SCI->getOpcode());
MachineBasicBlock::iterator MII = BB->end();
OpNum = EmitComparison(OpNum, SCI->getOperand(0), SCI->getOperand(1), BB,MII);
-
- const Type *CompTy = SCI->getOperand(0)->getType();
- bool isSigned = CompTy->isSigned() && getClassB(CompTy) != cFP;
- // LLVM -> X86 signed X86 unsigned
- // ----- ---------- ------------
- // seteq -> je je
- // setne -> jne jne
- // setlt -> jl jb
- // setge -> jge jae
- // setgt -> jg ja
- // setle -> jle jbe
-
- static const unsigned BITab[6] = { 2, 2, 0, 0, 1, 1 };
- unsigned BO_true = (OpNum % 2 == 0) ? 12 : 4;
- unsigned BO_false = (OpNum % 2 == 0) ? 4 : 12;
- unsigned BIval = BITab[0];
-
if (BI.getSuccessor(0) != NextBB) {
- BuildMI(BB, PPC32::BC, 3).addImm(BO_true).addImm(BIval).addMBB(MBBMap[BI.getSuccessor(0)]);
+ BuildMI(BB, Opcode, 2).addReg(PPC32::CR0)
+ .addMBB(MBBMap[BI.getSuccessor(0)]);
if (BI.getSuccessor(1) != NextBB)
- BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
+ BuildMI(BB, PPC32::B, 1).addMBB(MBBMap[BI.getSuccessor(1)]);
} else {
// Change to the inverse condition...
if (BI.getSuccessor(1) != NextBB) {
- BuildMI(BB, PPC32::BC, 3).addImm(BO_false).addImm(BIval).addMBB(MBBMap[BI.getSuccessor(1)]);
+ Opcode = invertPPCBranchOpcode(Opcode);
+ BuildMI(BB, Opcode, 2).addReg(PPC32::CR0)
+ .addMBB(MBBMap[BI.getSuccessor(1)]);
}
}
}
+static Constant* minUConstantForValue(uint64_t val) {
+ if (val <= 1)
+ return ConstantBool::get(val);
+ else if (ConstantUInt::isValueValidForType(Type::UShortTy, val))
+ return ConstantUInt::get(Type::UShortTy, val);
+ else if (ConstantUInt::isValueValidForType(Type::UIntTy, val))
+ return ConstantUInt::get(Type::UIntTy, val);
+ else if (ConstantUInt::isValueValidForType(Type::ULongTy, val))
+ return ConstantUInt::get(Type::ULongTy, val);
+
+ std::cerr << "Value: " << val << " not accepted for any integral type!\n";
+ abort();
+}
/// doCall - This emits an abstract call instruction, setting up the arguments
/// and the return value as appropriate. For the actual function call itself,
/// FIXME: See Documentation at the following URL for "correct" behavior
/// <http://developer.apple.com/documentation/DeveloperTools/Conceptual/MachORuntime/2rt_powerpc_abi/chapter_9_section_5.html>
void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
- const std::vector<ValueRecord> &Args) {
+ const std::vector<ValueRecord> &Args, bool isVarArg) {
// Count how many bytes are to be pushed on the stack...
unsigned NumBytes = 0;
NumBytes += 4; break;
case cLong:
NumBytes += 8; break;
- case cFP:
- NumBytes += Args[i].Ty == Type::FloatTy ? 4 : 8;
+ case cFP32:
+ NumBytes += 4; break;
+ case cFP64:
+ NumBytes += 8; break;
break;
default: assert(0 && "Unknown class!");
}
BuildMI(BB, PPC32::ADJCALLSTACKDOWN, 1).addImm(NumBytes);
// Arguments go on the stack in reverse order, as specified by the ABI.
- unsigned ArgOffset = 0;
- unsigned GPR_remaining = 8;
- unsigned FPR_remaining = 13;
- unsigned GPR_idx = 3;
- unsigned FPR_idx = 1;
-
+ // Offset to the paramater area on the stack is 24.
+ unsigned ArgOffset = 24;
+ int GPR_remaining = 8, FPR_remaining = 13;
+ unsigned GPR_idx = 0, FPR_idx = 0;
+ static const unsigned GPR[] = {
+ PPC32::R3, PPC32::R4, PPC32::R5, PPC32::R6,
+ PPC32::R7, PPC32::R8, PPC32::R9, PPC32::R10,
+ };
+ static const unsigned FPR[] = {
+ PPC32::F1, PPC32::F2, PPC32::F3, PPC32::F4, PPC32::F5, PPC32::F6,
+ PPC32::F7, PPC32::F8, PPC32::F9, PPC32::F10, PPC32::F11, PPC32::F12,
+ PPC32::F13
+ };
+
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
unsigned ArgReg;
switch (getClassB(Args[i].Ty)) {
// Promote arg to 32 bits wide into a temporary register...
ArgReg = makeAnotherReg(Type::UIntTy);
promote32(ArgReg, Args[i]);
-
- // Reg or stack?
- if (GPR_remaining > 0) {
- BuildMI(BB, PPC32::OR, 2, PPC32::R0 + GPR_idx).addReg(ArgReg).addReg(ArgReg);
- } else {
- BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset).addReg(PPC32::R1);
- }
- break;
+
+ // Reg or stack?
+ if (GPR_remaining > 0) {
+ BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
+ .addReg(ArgReg);
+ CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
+ } else {
+ BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset)
+ .addReg(PPC32::R1);
+ }
+ break;
case cInt:
ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
- // Reg or stack?
- if (GPR_remaining > 0) {
- BuildMI(BB, PPC32::OR, 2, PPC32::R0 + GPR_idx).addReg(ArgReg).addReg(ArgReg);
- } else {
- BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset).addReg(PPC32::R1);
- }
- break;
+ // Reg or stack?
+ if (GPR_remaining > 0) {
+ BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx]).addReg(ArgReg)
+ .addReg(ArgReg);
+ CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
+ } else {
+ BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset)
+ .addReg(PPC32::R1);
+ }
+ break;
case cLong:
- ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
+ ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
- // Reg or stack?
- if (GPR_remaining > 1) {
- BuildMI(BB, PPC32::OR, 2, PPC32::R0 + GPR_idx).addReg(ArgReg).addReg(ArgReg);
- BuildMI(BB, PPC32::OR, 2, PPC32::R0 + GPR_idx + 1).addReg(ArgReg+1).addReg(ArgReg+1);
- } else {
- BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset).addReg(PPC32::R1);
- BuildMI(BB, PPC32::STW, 3).addReg(ArgReg+1).addImm(ArgOffset+4).addReg(PPC32::R1);
- }
+ // Reg or stack? Note that PPC calling conventions state that long args
+ // are passed rN = hi, rN+1 = lo, opposite of LLVM.
+ if (GPR_remaining > 1) {
+ BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx]).addReg(ArgReg+1)
+ .addReg(ArgReg+1);
+ BuildMI(BB, PPC32::OR, 2, GPR[GPR_idx+1]).addReg(ArgReg)
+ .addReg(ArgReg);
+ CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
+ CallMI->addRegOperand(GPR[GPR_idx+1], MachineOperand::Use);
+ } else {
+ BuildMI(BB, PPC32::STW, 3).addReg(ArgReg).addImm(ArgOffset)
+ .addReg(PPC32::R1);
+ BuildMI(BB, PPC32::STW, 3).addReg(ArgReg+1).addImm(ArgOffset+4)
+ .addReg(PPC32::R1);
+ }
ArgOffset += 4; // 8 byte entry, not 4.
- if (GPR_remaining > 0) {
- GPR_remaining -= 1; // uses up 2 GPRs
- GPR_idx += 1;
- }
+ GPR_remaining -= 1; // uses up 2 GPRs
+ GPR_idx += 1;
break;
- case cFP:
+ case cFP32:
ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
- if (Args[i].Ty == Type::FloatTy) {
- // Reg or stack?
- if (FPR_remaining > 0) {
- BuildMI(BB, PPC32::FMR, 1, PPC32::F0 + FPR_idx).addReg(ArgReg);
- FPR_remaining--;
- FPR_idx++;
- } else {
- BuildMI(BB, PPC32::STFS, 3).addReg(ArgReg).addImm(ArgOffset).addReg(PPC32::R1);
- }
+ // Reg or stack?
+ if (FPR_remaining > 0) {
+ BuildMI(BB, PPC32::FMR, 1, FPR[FPR_idx]).addReg(ArgReg);
+ CallMI->addRegOperand(FPR[FPR_idx], MachineOperand::Use);
+ FPR_remaining--;
+ FPR_idx++;
+
+ // If this is a vararg function, and there are GPRs left, also
+ // pass the float in an int. Otherwise, put it on the stack.
+ if (isVarArg) {
+ BuildMI(BB, PPC32::STFS, 3).addReg(ArgReg).addImm(ArgOffset)
+ .addReg(PPC32::R1);
+ if (GPR_remaining > 0) {
+ BuildMI(BB, PPC32::LWZ, 2, GPR[GPR_idx])
+ .addImm(ArgOffset).addReg(ArgReg);
+ CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
+ }
+ }
} else {
- assert(Args[i].Ty == Type::DoubleTy && "Unknown FP type!");
- // Reg or stack?
- if (FPR_remaining > 0) {
- BuildMI(BB, PPC32::FMR, 1, PPC32::F0 + FPR_idx).addReg(ArgReg);
- FPR_remaining--;
- FPR_idx++;
- } else {
- BuildMI(BB, PPC32::STFD, 3).addReg(ArgReg).addImm(ArgOffset).addReg(PPC32::R1);
- }
-
- ArgOffset += 4; // 8 byte entry, not 4.
- if (GPR_remaining > 0) {
- GPR_remaining--; // uses up 2 GPRs
- GPR_idx++;
- }
+ BuildMI(BB, PPC32::STFS, 3).addReg(ArgReg).addImm(ArgOffset)
+ .addReg(PPC32::R1);
}
break;
-
+ case cFP64:
+ ArgReg = Args[i].Val ? getReg(Args[i].Val) : Args[i].Reg;
+ // Reg or stack?
+ if (FPR_remaining > 0) {
+ BuildMI(BB, PPC32::FMR, 1, FPR[FPR_idx]).addReg(ArgReg);
+ CallMI->addRegOperand(FPR[FPR_idx], MachineOperand::Use);
+ FPR_remaining--;
+ FPR_idx++;
+ // For vararg functions, must pass doubles via int regs as well
+ if (isVarArg) {
+ BuildMI(BB, PPC32::STFD, 3).addReg(ArgReg).addImm(ArgOffset)
+ .addReg(PPC32::R1);
+
+ if (GPR_remaining > 1) {
+ BuildMI(BB, PPC32::LWZ, 2, GPR[GPR_idx]).addImm(ArgOffset)
+ .addReg(PPC32::R1);
+ BuildMI(BB, PPC32::LWZ, 2, GPR[GPR_idx+1])
+ .addImm(ArgOffset+4).addReg(PPC32::R1);
+ CallMI->addRegOperand(GPR[GPR_idx], MachineOperand::Use);
+ CallMI->addRegOperand(GPR[GPR_idx+1], MachineOperand::Use);
+ }
+ }
+ } else {
+ BuildMI(BB, PPC32::STFD, 3).addReg(ArgReg).addImm(ArgOffset)
+ .addReg(PPC32::R1);
+ }
+ // Doubles use 8 bytes, and 2 GPRs worth of param space
+ ArgOffset += 4;
+ GPR_remaining--;
+ GPR_idx++;
+ break;
+
default: assert(0 && "Unknown class!");
}
ArgOffset += 4;
- if (GPR_remaining > 0) {
- GPR_remaining--; // uses up 2 GPRs
- GPR_idx++;
- }
+ GPR_remaining--;
+ GPR_idx++;
}
} else {
BuildMI(BB, PPC32::ADJCALLSTACKDOWN, 1).addImm(0);
}
BB->push_back(CallMI);
-
BuildMI(BB, PPC32::ADJCALLSTACKUP, 1).addImm(NumBytes);
// If there is a return value, scavenge the result from the location the call
case cShort:
case cInt:
// Integral results are in r3
- BuildMI(BB, PPC32::OR, 2, Ret.Reg).addReg(PPC32::R3).addReg(PPC32::R3);
- case cFP: // Floating-point return values live in f1
+ BuildMI(BB, PPC32::OR, 2, Ret.Reg).addReg(PPC32::R3).addReg(PPC32::R3);
+ break;
+ case cFP32: // Floating-point return values live in f1
+ case cFP64:
BuildMI(BB, PPC32::FMR, 1, Ret.Reg).addReg(PPC32::F1);
break;
- case cLong: // Long values are in r3:r4
- BuildMI(BB, PPC32::OR, 2, Ret.Reg).addReg(PPC32::R3).addReg(PPC32::R3);
- BuildMI(BB, PPC32::OR, 2, Ret.Reg+1).addReg(PPC32::R4).addReg(PPC32::R4);
+ case cLong: // Long values are in r3 hi:r4 lo
+ BuildMI(BB, PPC32::OR, 2, Ret.Reg+1).addReg(PPC32::R3).addReg(PPC32::R3);
+ BuildMI(BB, PPC32::OR, 2, Ret.Reg).addReg(PPC32::R4).addReg(PPC32::R4);
break;
default: assert(0 && "Unknown class!");
}
/// visitCallInst - Push args on stack and do a procedure call instruction.
void ISel::visitCallInst(CallInst &CI) {
MachineInstr *TheCall;
- if (Function *F = CI.getCalledFunction()) {
+ Function *F = CI.getCalledFunction();
+ if (F) {
// Is it an intrinsic function call?
if (Intrinsic::ID ID = (Intrinsic::ID)F->getIntrinsicID()) {
visitIntrinsicCall(ID, CI); // Special intrinsics are not handled here
TheCall = BuildMI(PPC32::CALLpcrel, 1).addGlobalAddress(F, true);
} else { // Emit an indirect call through the CTR
unsigned Reg = getReg(CI.getCalledValue());
- BuildMI(PPC32::MTSPR, 2).addZImm(9).addReg(Reg);
- TheCall = BuildMI(PPC32::CALLindirect, 1).addZImm(20).addZImm(0);
+ BuildMI(BB, PPC32::MTCTR, 1).addReg(Reg);
+ TheCall = BuildMI(PPC32::CALLindirect, 2).addZImm(20).addZImm(0);
}
std::vector<ValueRecord> Args;
Args.push_back(ValueRecord(CI.getOperand(i)));
unsigned DestReg = CI.getType() != Type::VoidTy ? getReg(CI) : 0;
- doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args);
+ bool isVarArg = F ? F->getFunctionType()->isVarArg() : true;
+ doCall(ValueRecord(DestReg, CI.getType()), TheCall, Args, isVarArg);
}
static Value *dyncastIsNan(Value *V) {
if (CallInst *CI = dyn_cast<CallInst>(V))
if (Function *F = CI->getCalledFunction())
- if (F->getIntrinsicID() == Intrinsic::isnan)
+ if (F->getIntrinsicID() == Intrinsic::isunordered)
return CI->getOperand(1);
return 0;
}
case Intrinsic::vaend:
case Intrinsic::returnaddress:
case Intrinsic::frameaddress:
- case Intrinsic::isnan:
+ // FIXME: should lower this ourselves
+ // case Intrinsic::isunordered:
// We directly implement these intrinsics
break;
case Intrinsic::readio: {
// On PPC, memory operations are in-order. Lower this intrinsic
// into a volatile store.
Instruction *Before = CI->getPrev();
- StoreInst *LI = new StoreInst(CI->getOperand(1),
+ StoreInst *SI = new StoreInst(CI->getOperand(1),
CI->getOperand(2), true, CI);
- CI->replaceAllUsesWith(LI);
+ CI->replaceAllUsesWith(SI);
BB->getInstList().erase(CI);
break;
}
case Intrinsic::vastart:
// Get the address of the first vararg value...
TmpReg1 = getReg(CI);
- addFrameReference(BuildMI(BB, PPC32::ADDI, 2, TmpReg1), VarArgsFrameIndex);
+ addFrameReference(BuildMI(BB, PPC32::ADDI, 2, TmpReg1), VarArgsFrameIndex,
+ 0, false);
return;
case Intrinsic::vacopy:
case Intrinsic::vaend: return;
case Intrinsic::returnaddress:
+ TmpReg1 = getReg(CI);
+ if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
+ MachineFrameInfo *MFI = F->getFrameInfo();
+ unsigned NumBytes = MFI->getStackSize();
+
+ BuildMI(BB, PPC32::LWZ, 2, TmpReg1).addImm(NumBytes+8)
+ .addReg(PPC32::R1);
+ } else {
+ // Values other than zero are not implemented yet.
+ BuildMI(BB, PPC32::LI, 1, TmpReg1).addImm(0);
+ }
+ return;
+
case Intrinsic::frameaddress:
TmpReg1 = getReg(CI);
if (cast<Constant>(CI.getOperand(1))->isNullValue()) {
- if (ID == Intrinsic::returnaddress) {
- // Just load the return address
- addFrameReference(BuildMI(BB, PPC32::LWZ, 2, TmpReg1),
- ReturnAddressIndex);
- } else {
- addFrameReference(BuildMI(BB, PPC32::ADDI, 2, TmpReg1),
- ReturnAddressIndex, -4, false);
- }
+ BuildMI(BB, PPC32::OR, 2, TmpReg1).addReg(PPC32::R1).addReg(PPC32::R1);
} else {
// Values other than zero are not implemented yet.
- BuildMI(BB, PPC32::ADDI, 2, TmpReg1).addReg(PPC32::R0).addImm(0);
+ BuildMI(BB, PPC32::LI, 1, TmpReg1).addImm(0);
}
return;
+#if 0
+ // This may be useful for supporting isunordered
case Intrinsic::isnan:
// If this is only used by 'isunordered' style comparisons, don't emit it.
if (isOnlyUsedByUnorderedComparisons(&CI)) return;
TmpReg1 = getReg(CI.getOperand(1));
emitUCOM(BB, BB->end(), TmpReg1, TmpReg1);
- TmpReg2 = makeAnotherReg(Type::IntTy);
- BuildMI(BB, PPC32::MFCR, TmpReg2);
+ TmpReg2 = makeAnotherReg(Type::IntTy);
+ BuildMI(BB, PPC32::MFCR, TmpReg2);
TmpReg3 = getReg(CI);
BuildMI(BB, PPC32::RLWINM, 4, TmpReg3).addReg(TmpReg2).addImm(4).addImm(31).addImm(31);
return;
-
+#endif
+
default: assert(0 && "Error: unknown intrinsics should have been lowered!");
}
}
// Special case: op Reg, <const fp>
if (ConstantFP *Op1C = dyn_cast<ConstantFP>(Op1)) {
- // Create a constant pool entry for this constant.
- MachineConstantPool *CP = F->getConstantPool();
- unsigned CPI = CP->getConstantPoolIndex(Op1C);
- const Type *Ty = Op1->getType();
-
- static const unsigned OpcodeTab[][4] = {
- { PPC32::FADDS, PPC32::FSUBS, PPC32::FMULS, PPC32::FDIVS }, // Float
- { PPC32::FADD, PPC32::FSUB, PPC32::FMUL, PPC32::FDIV }, // Double
- };
-
- assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
- unsigned TempReg = makeAnotherReg(Ty);
- unsigned LoadOpcode = Ty == Type::FloatTy ? PPC32::LFS : PPC32::LFD;
- addConstantPoolReference(BuildMI(*BB, IP, LoadOpcode, 2, TempReg), CPI);
+ // Create a constant pool entry for this constant.
+ MachineConstantPool *CP = F->getConstantPool();
+ unsigned CPI = CP->getConstantPoolIndex(Op1C);
+ const Type *Ty = Op1->getType();
+ assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
+
+ static const unsigned OpcodeTab[][4] = {
+ { PPC32::FADDS, PPC32::FSUBS, PPC32::FMULS, PPC32::FDIVS }, // Float
+ { PPC32::FADD, PPC32::FSUB, PPC32::FMUL, PPC32::FDIV }, // Double
+ };
- unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
- unsigned Op0r = getReg(Op0, BB, IP);
- BuildMI(*BB, IP, Opcode, DestReg).addReg(Op0r).addReg(TempReg);
- return;
- }
+ unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
+ unsigned Op1Reg = getReg(Op1C, BB, IP);
+ unsigned Op0r = getReg(Op0, BB, IP);
+ BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1Reg);
+ return;
+ }
// Special case: R1 = op <const fp>, R2
- if (ConstantFP *CFP = dyn_cast<ConstantFP>(Op0))
- if (CFP->isExactlyValue(-0.0) && OperatorClass == 1) {
+ if (ConstantFP *Op0C = dyn_cast<ConstantFP>(Op0))
+ if (Op0C->isExactlyValue(-0.0) && OperatorClass == 1) {
// -0.0 - X === -X
unsigned op1Reg = getReg(Op1, BB, IP);
BuildMI(*BB, IP, PPC32::FNEG, 1, DestReg).addReg(op1Reg);
// Create a constant pool entry for this constant.
MachineConstantPool *CP = F->getConstantPool();
- unsigned CPI = CP->getConstantPoolIndex(CFP);
- const Type *Ty = CFP->getType();
+ unsigned CPI = CP->getConstantPoolIndex(Op0C);
+ const Type *Ty = Op0C->getType();
+ assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
static const unsigned OpcodeTab[][4] = {
- { PPC32::FADDS, PPC32::FSUBS, PPC32::FMULS, PPC32::FDIVS }, // Float
- { PPC32::FADD, PPC32::FSUB, PPC32::FMUL, PPC32::FDIV }, // Double
+ { PPC32::FADDS, PPC32::FSUBS, PPC32::FMULS, PPC32::FDIVS }, // Float
+ { PPC32::FADD, PPC32::FSUB, PPC32::FMUL, PPC32::FDIV }, // Double
};
- assert(Ty == Type::FloatTy || Ty == Type::DoubleTy && "Unknown FP type!");
- unsigned TempReg = makeAnotherReg(Ty);
- unsigned LoadOpcode = Ty == Type::FloatTy ? PPC32::LFS : PPC32::LFD;
- addConstantPoolReference(BuildMI(*BB, IP, LoadOpcode, 2, TempReg), CPI);
-
unsigned Opcode = OpcodeTab[Ty != Type::FloatTy][OperatorClass];
- unsigned Op1r = getReg(Op1, BB, IP);
- BuildMI(*BB, IP, Opcode, DestReg).addReg(TempReg).addReg(Op1r);
+ unsigned Op0Reg = getReg(Op0C, BB, IP);
+ unsigned Op1Reg = getReg(Op1, BB, IP);
+ BuildMI(*BB, IP, Opcode, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
return;
}
// General case.
- static const unsigned OpcodeTab[4] = {
+ static const unsigned OpcodeTab[] = {
PPC32::FADD, PPC32::FSUB, PPC32::FMUL, PPC32::FDIV
};
unsigned OperatorClass, unsigned DestReg) {
unsigned Class = getClassB(Op0->getType());
- // Arithmetic and Bitwise operators
- static const unsigned OpcodeTab[5] = {
- PPC32::ADD, PPC32::SUB, PPC32::AND, PPC32::OR, PPC32::XOR
- };
- // Otherwise, code generate the full operation with a constant.
- static const unsigned BottomTab[] = {
- PPC32::ADDC, PPC32::SUBC, PPC32::AND, PPC32::OR, PPC32::XOR
- };
- static const unsigned TopTab[] = {
- PPC32::ADDE, PPC32::SUBFE, PPC32::AND, PPC32::OR, PPC32::XOR
- };
+ // Arithmetic and Bitwise operators
+ static const unsigned OpcodeTab[] = {
+ PPC32::ADD, PPC32::SUB, PPC32::AND, PPC32::OR, PPC32::XOR
+ };
+ // Otherwise, code generate the full operation with a constant.
+ static const unsigned BottomTab[] = {
+ PPC32::ADDC, PPC32::SUBC, PPC32::AND, PPC32::OR, PPC32::XOR
+ };
+ static const unsigned TopTab[] = {
+ PPC32::ADDE, PPC32::SUBFE, PPC32::AND, PPC32::OR, PPC32::XOR
+ };
- if (Class == cFP) {
+ if (Class == cFP32 || Class == cFP64) {
assert(OperatorClass < 2 && "No logical ops for FP!");
emitBinaryFPOperation(MBB, IP, Op0, Op1, OperatorClass, DestReg);
return;
if (Value *LHS = dyncastIsNan(Op0))
if (Value *RHS = dyncastIsNan(Op1)) {
unsigned Op0Reg = getReg(RHS, MBB, IP), Op1Reg = getReg(LHS, MBB, IP);
- unsigned TmpReg = makeAnotherReg(Type::IntTy);
+ unsigned TmpReg = makeAnotherReg(Type::IntTy);
emitUCOM(MBB, IP, Op0Reg, Op1Reg);
- BuildMI(*MBB, IP, PPC32::MFCR, TmpReg);
- BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(TmpReg).addImm(4).addImm(31).addImm(31);
+ BuildMI(*MBB, IP, PPC32::MFCR, TmpReg);
+ BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(TmpReg).addImm(4)
+ .addImm(31).addImm(31);
return;
}
}
BuildMI(*MBB, IP, PPC32::NEG, 1, DestReg).addReg(op1Reg);
if (Class == cLong) {
- unsigned zeroes = makeAnotherReg(Type::IntTy);
- unsigned overflow = makeAnotherReg(Type::IntTy);
+ unsigned zeroes = makeAnotherReg(Type::IntTy);
+ unsigned overflow = makeAnotherReg(Type::IntTy);
unsigned T = makeAnotherReg(Type::IntTy);
- BuildMI(*MBB, IP, PPC32::CNTLZW, 1, zeroes).addReg(op1Reg);
- BuildMI(*MBB, IP, PPC32::RLWINM, 4, overflow).addReg(zeroes).addImm(27).addImm(5).addImm(31);
- BuildMI(*MBB, IP, PPC32::ADD, 2, T).addReg(op1Reg+1).addReg(overflow);
- BuildMI(*MBB, IP, PPC32::NEG, 1, DestReg+1).addReg(T);
+ BuildMI(*MBB, IP, PPC32::CNTLZW, 1, zeroes).addReg(op1Reg);
+ BuildMI(*MBB, IP, PPC32::RLWINM, 4, overflow).addReg(zeroes).addImm(27)
+ .addImm(5).addImm(31);
+ BuildMI(*MBB, IP, PPC32::ADD, 2, T).addReg(op1Reg+1).addReg(overflow);
+ BuildMI(*MBB, IP, PPC32::NEG, 1, DestReg+1).addReg(T);
}
return;
}
if (OperatorClass == 4 && Op1C->isAllOnesValue()) {
BuildMI(*MBB, IP, PPC32::NOR, 2, DestReg).addReg(Op0r).addReg(Op0r);
if (Class == cLong) // Invert the top part too
- BuildMI(*MBB, IP, PPC32::NOR, 2, DestReg+1).addReg(Op0r+1).addReg(Op0r+1);
+ BuildMI(*MBB, IP, PPC32::NOR, 2, DestReg+1).addReg(Op0r+1)
+ .addReg(Op0r+1);
return;
}
if (OperatorClass != 2) // All but and...
BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(Op0r).addReg(Op0r);
else
- BuildMI(*MBB, IP, PPC32::ADDI, 2, DestReg).addReg(PPC32::R0).addImm(0);
- BuildMI(*MBB, IP, Opcode, 2, DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
+ BuildMI(*MBB, IP, PPC32::LI, 1, DestReg).addImm(0);
+ BuildMI(*MBB, IP, Opcode, 2, DestReg+1).addReg(Op0r+1).addReg(Op1r+1);
return;
}
if (Op1h == 0 && OperatorClass > 1) {
BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
if (OperatorClass != 2) // All but and
- BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(Op0r+1).addReg(Op0r+1);
+ BuildMI(*MBB, IP, PPC32::OR, 2,DestReg+1).addReg(Op0r+1).addReg(Op0r+1);
else
- BuildMI(*MBB, IP, PPC32::ADDI, 2, DestReg+1).addReg(PPC32::R0).addImm(0);
+ BuildMI(*MBB, IP, PPC32::LI, 1,DestReg+1).addImm(0);
return;
}
// TODO: We could handle lots of other special cases here, such as AND'ing
// with 0xFFFFFFFF00000000 -> noop, etc.
- BuildMI(*MBB, IP, BottomTab[OperatorClass], 2, DestReg).addReg(Op0r).addImm(Op1r);
- BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1).addReg(Op0r+1).addImm(Op1r+1);
+ BuildMI(*MBB, IP, BottomTab[OperatorClass], 2, DestReg).addReg(Op0r)
+ .addReg(Op1r);
+ BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1).addReg(Op0r+1)
+ .addReg(Op1r+1);
return;
}
unsigned Op1r = getReg(Op1, MBB, IP);
if (Class != cLong) {
- unsigned Opcode = OpcodeTab[OperatorClass];
- BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
+ unsigned Opcode = OpcodeTab[OperatorClass];
+ BuildMI(*MBB, IP, Opcode, 2, DestReg).addReg(Op0r).addReg(Op1r);
} else {
- BuildMI(*MBB, IP, BottomTab[OperatorClass], 2, DestReg).addReg(Op0r).addImm(Op1r);
- BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1).addReg(Op0r+1).addImm(Op1r+1);
+ BuildMI(*MBB, IP, BottomTab[OperatorClass], 2, DestReg).addReg(Op0r)
+ .addReg(Op1r);
+ BuildMI(*MBB, IP, TopTab[OperatorClass], 2, DestReg+1).addReg(Op0r+1)
+ .addReg(Op1r+1);
}
return;
}
unsigned Class = getClass(DestTy);
switch (Class) {
case cLong:
- BuildMI(*MBB, MBBI, PPC32::MULHW, 2, DestReg+1).addReg(op0Reg+1).addReg(op1Reg+1);
+ BuildMI(*MBB, MBBI, PPC32::MULHW, 2, DestReg+1).addReg(op0Reg+1)
+ .addReg(op1Reg+1);
case cInt:
case cShort:
case cByte:
BuildMI(*MBB, MBBI, PPC32::MULLW, 2, DestReg).addReg(op0Reg).addReg(op1Reg);
return;
default:
- assert(0 && "doMultiply cannot operate on unknown type!");
+ assert(0 && "doMultiply cannot operate on unknown type!");
}
}
/// doMultiplyConst - This function is specialized to efficiently codegen an 8,
/// 16, or 32-bit integer multiply by a constant.
+///
void ISel::doMultiplyConst(MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
unsigned DestReg, const Type *DestTy,
// Handle special cases here.
switch (ConstRHS) {
case 0:
- BuildMI(*MBB, IP, PPC32::ADDI, 2, DestReg).addReg(PPC32::R0).addImm(0);
+ BuildMI(*MBB, IP, PPC32::LI, 1, DestReg).addImm(0);
return;
case 1:
BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(op0Reg).addReg(op0Reg);
case cByte:
case cShort:
case cInt:
- BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(op0Reg).addImm(Shift-1).addImm(0).addImm(31-Shift-1);
+ BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(op0Reg)
+ .addImm(Shift-1).addImm(0).addImm(31-Shift+1);
return;
}
}
// Most general case, emit a normal multiply...
- unsigned TmpReg1 = makeAnotherReg(Type::IntTy);
- unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
- BuildMI(*MBB, IP, PPC32::ADDIS, 2, TmpReg1).addReg(PPC32::R0).addImm(ConstRHS >> 16);
- BuildMI(*MBB, IP, PPC32::ORI, 2, TmpReg2).addReg(TmpReg1).addImm(ConstRHS);
-
- // Emit a MUL to multiply the register holding the index by
- // elementSize, putting the result in OffsetReg.
- doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg2);
+ unsigned TmpReg = makeAnotherReg(Type::IntTy);
+ Constant *C = ConstantUInt::get(Type::UIntTy, ConstRHS);
+
+ copyConstantToRegister(MBB, IP, C, TmpReg);
+ doMultiply(MBB, IP, DestReg, DestTy, op0Reg, TmpReg);
}
void ISel::visitMul(BinaryOperator &I) {
doMultiply(&BB, IP, DestReg, Op1->getType(), Op0Reg, Op1Reg);
}
return;
- case cFP:
+ case cFP32:
+ case cFP64:
emitBinaryFPOperation(MBB, IP, Op0, Op1, 2, DestReg);
return;
case cLong:
if (CLow == 0) {
// If the low part of the constant is all zeros, things are simple.
- BuildMI(BB, IP, PPC32::ADDI, 2, DestReg).addReg(PPC32::R0).addImm(0);
+ BuildMI(BB, IP, PPC32::LI, 1, DestReg).addImm(0);
doMultiplyConst(&BB, IP, DestReg+1, Type::UIntTy, Op0Reg, CHi);
return;
}
if (CLow == 1) {
BuildMI(BB, IP, PPC32::OR, 2, DestReg).addReg(Op0Reg).addReg(Op0Reg);
} else {
- unsigned TmpRegL = makeAnotherReg(Type::UIntTy);
+ unsigned TmpRegL = makeAnotherReg(Type::UIntTy);
unsigned Op1RegL = makeAnotherReg(Type::UIntTy);
OverflowReg = makeAnotherReg(Type::UIntTy);
- BuildMI(BB, IP, PPC32::ADDIS, 2, TmpRegL).addReg(PPC32::R0).addImm(CLow >> 16);
- BuildMI(BB, IP, PPC32::ORI, 2, Op1RegL).addReg(TmpRegL).addImm(CLow);
- BuildMI(BB, IP, PPC32::MULLW, 2, DestReg).addReg(Op0Reg).addReg(Op1RegL);
- BuildMI(BB, IP, PPC32::MULHW, 2, OverflowReg).addReg(Op0Reg).addReg(Op1RegL);
+ BuildMI(BB, IP, PPC32::LIS, 1, TmpRegL).addImm(CLow >> 16);
+ BuildMI(BB, IP, PPC32::ORI, 2, Op1RegL).addReg(TmpRegL).addImm(CLow);
+ BuildMI(BB, IP, PPC32::MULLW, 2, DestReg).addReg(Op0Reg).addReg(Op1RegL);
+ BuildMI(BB, IP, PPC32::MULHW, 2, OverflowReg).addReg(Op0Reg)
+ .addReg(Op1RegL);
}
unsigned AHBLReg = makeAnotherReg(Type::UIntTy);
unsigned AHBLplusOverflowReg;
if (OverflowReg) {
AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
- BuildMI(BB, IP, PPC32::ADD, 2, // AH*BL+(AL*BL >> 32)
+ BuildMI(BB, IP, PPC32::ADD, 2,
AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
} else {
AHBLplusOverflowReg = AHBLReg;
}
if (CHi == 0) {
- BuildMI(BB, IP, PPC32::OR, 2, DestReg+1).addReg(AHBLplusOverflowReg).addReg(AHBLplusOverflowReg);
+ BuildMI(BB, IP, PPC32::OR, 2, DestReg+1).addReg(AHBLplusOverflowReg)
+ .addReg(AHBLplusOverflowReg);
} else {
- unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
+ unsigned ALBHReg = makeAnotherReg(Type::UIntTy);
doMultiplyConst(&BB, IP, ALBHReg, Type::UIntTy, Op0Reg, CHi);
- BuildMI(BB, IP, PPC32::ADD, 2, // AL*BH + AH*BL + (AL*BL >> 32)
+ BuildMI(BB, IP, PPC32::ADD, 2,
DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
}
return;
unsigned Op1Reg = getReg(Op1, &BB, IP);
- // Multiply the two low parts... capturing carry into EDX
- BuildMI(BB, IP, PPC32::MULLW, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg); // AL*BL
+ // Multiply the two low parts...
+ BuildMI(BB, IP, PPC32::MULLW, 2, DestReg).addReg(Op0Reg).addReg(Op1Reg);
unsigned OverflowReg = makeAnotherReg(Type::UIntTy);
- BuildMI(BB, IP, PPC32::MULHW, 2, OverflowReg).addReg(Op0Reg).addReg(Op1Reg); // AL*BL >> 32
+ BuildMI(BB, IP, PPC32::MULHW, 2, OverflowReg).addReg(Op0Reg).addReg(Op1Reg);
- unsigned AHBLReg = makeAnotherReg(Type::UIntTy); // AH*BL
+ unsigned AHBLReg = makeAnotherReg(Type::UIntTy);
BuildMI(BB, IP, PPC32::MULLW, 2, AHBLReg).addReg(Op0Reg+1).addReg(Op1Reg);
unsigned AHBLplusOverflowReg = makeAnotherReg(Type::UIntTy);
- BuildMI(BB, IP, PPC32::ADD, 2, // AH*BL+(AL*BL >> 32)
- AHBLplusOverflowReg).addReg(AHBLReg).addReg(OverflowReg);
+ BuildMI(BB, IP, PPC32::ADD, 2, AHBLplusOverflowReg).addReg(AHBLReg)
+ .addReg(OverflowReg);
unsigned ALBHReg = makeAnotherReg(Type::UIntTy); // AL*BH
BuildMI(BB, IP, PPC32::MULLW, 2, ALBHReg).addReg(Op0Reg).addReg(Op1Reg+1);
- BuildMI(BB, IP, PPC32::ADD, 2, // AL*BH + AH*BL + (AL*BL >> 32)
+ BuildMI(BB, IP, PPC32::ADD, 2,
DestReg+1).addReg(AHBLplusOverflowReg).addReg(ALBHReg);
}
Value *Op0 = I.getOperand(0), *Op1 = I.getOperand(1);
MachineBasicBlock::iterator IP = BB->end();
- emitDivRemOperation(BB, IP, Op0, Op1, I.getOpcode() == Instruction::Div, ResultReg);
+ emitDivRemOperation(BB, IP, Op0, Op1, I.getOpcode() == Instruction::Div,
+ ResultReg);
}
void ISel::emitDivRemOperation(MachineBasicBlock *BB,
const Type *Ty = Op0->getType();
unsigned Class = getClass(Ty);
switch (Class) {
- case cFP: // Floating point divide
+ case cFP32:
if (isDiv) {
+ // Floating point divide...
emitBinaryFPOperation(BB, IP, Op0, Op1, 3, ResultReg);
return;
- } else { // Floating point remainder...
+ } else {
+ // Floating point remainder via fmodf(float x, float y);
unsigned Op0Reg = getReg(Op0, BB, IP);
unsigned Op1Reg = getReg(Op1, BB, IP);
MachineInstr *TheCall =
- BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("fmod", true);
+ BuildMI(PPC32::CALLpcrel, 1).addGlobalAddress(fmodfFn, true);
+ std::vector<ValueRecord> Args;
+ Args.push_back(ValueRecord(Op0Reg, Type::FloatTy));
+ Args.push_back(ValueRecord(Op1Reg, Type::FloatTy));
+ doCall(ValueRecord(ResultReg, Type::FloatTy), TheCall, Args, false);
+ }
+ return;
+ case cFP64:
+ if (isDiv) {
+ // Floating point divide...
+ emitBinaryFPOperation(BB, IP, Op0, Op1, 3, ResultReg);
+ return;
+ } else {
+ // Floating point remainder via fmod(double x, double y);
+ unsigned Op0Reg = getReg(Op0, BB, IP);
+ unsigned Op1Reg = getReg(Op1, BB, IP);
+ MachineInstr *TheCall =
+ BuildMI(PPC32::CALLpcrel, 1).addGlobalAddress(fmodFn, true);
std::vector<ValueRecord> Args;
Args.push_back(ValueRecord(Op0Reg, Type::DoubleTy));
Args.push_back(ValueRecord(Op1Reg, Type::DoubleTy));
- doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args);
+ doCall(ValueRecord(ResultReg, Type::DoubleTy), TheCall, Args, false);
}
return;
case cLong: {
- static const char *FnName[] =
- { "__moddi3", "__divdi3", "__umoddi3", "__udivdi3" };
+ static Function* const Funcs[] =
+ { __moddi3Fn, __divdi3Fn, __umoddi3Fn, __udivdi3Fn };
unsigned Op0Reg = getReg(Op0, BB, IP);
unsigned Op1Reg = getReg(Op1, BB, IP);
unsigned NameIdx = Ty->isUnsigned()*2 + isDiv;
MachineInstr *TheCall =
- BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol(FnName[NameIdx], true);
+ BuildMI(PPC32::CALLpcrel, 1).addGlobalAddress(Funcs[NameIdx], true);
std::vector<ValueRecord> Args;
Args.push_back(ValueRecord(Op0Reg, Type::LongTy));
Args.push_back(ValueRecord(Op1Reg, Type::LongTy));
- doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args);
+ doCall(ValueRecord(ResultReg, Type::LongTy), TheCall, Args, false);
return;
}
case cByte: case cShort: case cInt:
return;
}
- bool isNeg = false;
- if (V < 0) { // Not a positive power of 2?
- V = -V;
- isNeg = true; // Maybe it's a negative power of 2.
- }
- if (unsigned Log = ExactLog2(V)) {
- --Log;
+ unsigned log2V = ExactLog2(V);
+ if (log2V != 0 && Ty->isSigned()) {
unsigned Op0Reg = getReg(Op0, BB, IP);
unsigned TmpReg = makeAnotherReg(Op0->getType());
- if (Log != 1)
- BuildMI(*BB, IP, PPC32::SRAWI, 2, TmpReg).addReg(Op0Reg).addImm(Log-1);
- else
- BuildMI(*BB, IP, PPC32::OR, 2, TmpReg).addReg(Op0Reg).addReg(Op0Reg);
-
- unsigned TmpReg2 = makeAnotherReg(Op0->getType());
- BuildMI(*BB, IP, PPC32::RLWINM, 4, TmpReg2).addReg(TmpReg).addImm(Log).addImm(32-Log).addImm(31);
-
- unsigned TmpReg3 = makeAnotherReg(Op0->getType());
- BuildMI(*BB, IP, PPC32::ADD, 2, TmpReg3).addReg(Op0Reg).addReg(TmpReg2);
-
- unsigned TmpReg4 = isNeg ? makeAnotherReg(Op0->getType()) : ResultReg;
- BuildMI(*BB, IP, PPC32::SRAWI, 2, TmpReg4).addReg(Op0Reg).addImm(Log);
-
- if (isNeg)
- BuildMI(*BB, IP, PPC32::NEG, 1, ResultReg).addReg(TmpReg4);
+
+ BuildMI(*BB, IP, PPC32::SRAWI, 2, TmpReg).addReg(Op0Reg)
+ .addImm(log2V-1);
+ BuildMI(*BB, IP, PPC32::ADDZE, 1, ResultReg).addReg(TmpReg);
return;
}
}
unsigned Op0Reg = getReg(Op0, BB, IP);
unsigned Op1Reg = getReg(Op1, BB, IP);
-
+ unsigned Opcode = Ty->isSigned() ? PPC32::DIVW : PPC32::DIVWU;
+
if (isDiv) {
- if (Ty->isSigned()) {
- BuildMI(*BB, IP, PPC32::DIVW, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
- } else {
- BuildMI(*BB, IP, PPC32::DIVWU, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
- }
+ BuildMI(*BB, IP, Opcode, 2, ResultReg).addReg(Op0Reg).addReg(Op1Reg);
} else { // Remainder
- unsigned TmpReg1 = makeAnotherReg(Op0->getType());
- unsigned TmpReg2 = makeAnotherReg(Op0->getType());
-
- if (Ty->isSigned()) {
- BuildMI(*BB, IP, PPC32::DIVW, 2, TmpReg1).addReg(Op0Reg).addReg(Op1Reg);
- } else {
- BuildMI(*BB, IP, PPC32::DIVWU, 2, TmpReg1).addReg(Op0Reg).addReg(Op1Reg);
- }
- BuildMI(*BB, IP, PPC32::MULLW, 2, TmpReg2).addReg(TmpReg1).addReg(Op1Reg);
- BuildMI(*BB, IP, PPC32::SUBF, 2, ResultReg).addReg(TmpReg2).addReg(Op0Reg);
+ unsigned TmpReg1 = makeAnotherReg(Op0->getType());
+ unsigned TmpReg2 = makeAnotherReg(Op0->getType());
+
+ BuildMI(*BB, IP, Opcode, 2, TmpReg1).addReg(Op0Reg).addReg(Op1Reg);
+ BuildMI(*BB, IP, PPC32::MULLW, 2, TmpReg2).addReg(TmpReg1).addReg(Op1Reg);
+ BuildMI(*BB, IP, PPC32::SUBF, 2, ResultReg).addReg(TmpReg2).addReg(Op0Reg);
}
}
///
void ISel::visitShiftInst(ShiftInst &I) {
MachineBasicBlock::iterator IP = BB->end ();
- emitShiftOperation (BB, IP, I.getOperand (0), I.getOperand (1),
- I.getOpcode () == Instruction::Shl, I.getType (),
- getReg (I));
+ emitShiftOperation(BB, IP, I.getOperand (0), I.getOperand (1),
+ I.getOpcode () == Instruction::Shl, I.getType (),
+ getReg (I));
}
/// emitShiftOperation - Common code shared between visitShiftInst and
/// constant expression support.
+///
void ISel::emitShiftOperation(MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
Value *Op, Value *ShiftAmount, bool isLeftShift,
unsigned Amount = CUI->getValue();
if (Amount < 32) {
if (isLeftShift) {
- // FIXME: RLWIMI is a use-and-def of DestReg+1, but that violates SSA
- BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg+1).addReg(SrcReg+1).addImm(Amount).addImm(0).addImm(31-Amount);
- BuildMI(*MBB, IP, PPC32::RLWIMI, 5).addReg(DestReg+1).addReg(SrcReg).addImm(Amount).addImm(32-Amount).addImm(31);
- BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg).addImm(Amount).addImm(0).addImm(31-Amount);
+ // FIXME: RLWIMI is a use-and-def of DestReg+1, but that violates SSA
+ BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg+1).addReg(SrcReg+1)
+ .addImm(Amount).addImm(0).addImm(31-Amount);
+ BuildMI(*MBB, IP, PPC32::RLWIMI, 5).addReg(DestReg+1).addReg(SrcReg)
+ .addImm(Amount).addImm(32-Amount).addImm(31);
+ BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg)
+ .addImm(Amount).addImm(0).addImm(31-Amount);
} else {
- // FIXME: RLWIMI is a use-and-def of DestReg, but that violates SSA
- BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg).addImm(32-Amount).addImm(Amount).addImm(31);
- BuildMI(*MBB, IP, PPC32::RLWIMI, 5).addReg(DestReg).addReg(SrcReg+1).addImm(32-Amount).addImm(0).addImm(Amount-1);
- BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg+1).addReg(SrcReg+1).addImm(32-Amount).addImm(Amount).addImm(31);
+ // FIXME: RLWIMI is a use-and-def of DestReg, but that violates SSA
+ BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg)
+ .addImm(32-Amount).addImm(Amount).addImm(31);
+ BuildMI(*MBB, IP, PPC32::RLWIMI, 5).addReg(DestReg).addReg(SrcReg+1)
+ .addImm(32-Amount).addImm(0).addImm(Amount-1);
+ BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg+1).addReg(SrcReg+1)
+ .addImm(32-Amount).addImm(Amount).addImm(31);
}
} else { // Shifting more than 32 bits
Amount -= 32;
if (isLeftShift) {
if (Amount != 0) {
- BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg+1).addReg(SrcReg).addImm(Amount).addImm(0).addImm(31-Amount);
+ BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg+1).addReg(SrcReg)
+ .addImm(Amount).addImm(0).addImm(31-Amount);
} else {
- BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(SrcReg).addReg(SrcReg);
+ BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(SrcReg)
+ .addReg(SrcReg);
}
- BuildMI(*MBB, IP, PPC32::ADDI, 2, DestReg).addReg(PPC32::R0).addImm(0);
+ BuildMI(*MBB, IP, PPC32::LI, 1, DestReg).addImm(0);
} else {
if (Amount != 0) {
- if (isSigned)
- BuildMI(*MBB, IP, PPC32::SRAWI, 2, DestReg).addReg(SrcReg+1).addImm(Amount);
- else
- BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg+1).addImm(32-Amount).addImm(Amount).addImm(31);
+ if (isSigned)
+ BuildMI(*MBB, IP, PPC32::SRAWI, 2, DestReg).addReg(SrcReg+1)
+ .addImm(Amount);
+ else
+ BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg+1)
+ .addImm(32-Amount).addImm(Amount).addImm(31);
} else {
- BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg+1).addReg(SrcReg+1);
+ BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg+1)
+ .addReg(SrcReg+1);
}
- BuildMI(*MBB, IP, PPC32::ADDI, 2, DestReg+1).addReg(PPC32::R0).addImm(0);
+ BuildMI(*MBB, IP,PPC32::LI,1,DestReg+1).addImm(0);
}
}
} else {
unsigned TmpReg1 = makeAnotherReg(Type::IntTy);
unsigned TmpReg2 = makeAnotherReg(Type::IntTy);
- unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
- unsigned TmpReg4 = makeAnotherReg(Type::IntTy);
- unsigned TmpReg5 = makeAnotherReg(Type::IntTy);
- unsigned TmpReg6 = makeAnotherReg(Type::IntTy);
- unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
-
+ unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
+ unsigned TmpReg4 = makeAnotherReg(Type::IntTy);
+ unsigned TmpReg5 = makeAnotherReg(Type::IntTy);
+ unsigned TmpReg6 = makeAnotherReg(Type::IntTy);
+ unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
+
if (isLeftShift) {
- BuildMI(*MBB, IP, PPC32::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg).addImm(32);
- BuildMI(*MBB, IP, PPC32::SLW, 2, TmpReg2).addReg(SrcReg+1).addReg(ShiftAmountReg);
- BuildMI(*MBB, IP, PPC32::SRW, 2, TmpReg3).addReg(SrcReg).addReg(TmpReg1);
- BuildMI(*MBB, IP, PPC32::OR, 2, TmpReg4).addReg(TmpReg2).addReg(TmpReg3);
- BuildMI(*MBB, IP, PPC32::ADDI, 2, TmpReg5).addReg(ShiftAmountReg).addImm(-32);
- BuildMI(*MBB, IP, PPC32::SLW, 2, TmpReg6).addReg(SrcReg).addReg(TmpReg5);
- BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(TmpReg4).addReg(TmpReg6);
- BuildMI(*MBB, IP, PPC32::SLW, 2, DestReg).addReg(SrcReg).addReg(ShiftAmountReg);
- } else {
- if (isSigned) {
- // FIXME: Unimplmented
- // Page C-3 of the PowerPC 32bit Programming Environments Manual
- } else {
- BuildMI(*MBB, IP, PPC32::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg).addImm(32);
- BuildMI(*MBB, IP, PPC32::SRW, 2, TmpReg2).addReg(SrcReg).addReg(ShiftAmountReg);
- BuildMI(*MBB, IP, PPC32::SLW, 2, TmpReg3).addReg(SrcReg+1).addReg(TmpReg1);
- BuildMI(*MBB, IP, PPC32::OR, 2, TmpReg4).addReg(TmpReg2).addReg(TmpReg3);
- BuildMI(*MBB, IP, PPC32::ADDI, 2, TmpReg5).addReg(ShiftAmountReg).addImm(-32);
- BuildMI(*MBB, IP, PPC32::SRW, 2, TmpReg6).addReg(SrcReg+1).addReg(TmpReg5);
- BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(TmpReg4).addReg(TmpReg6);
- BuildMI(*MBB, IP, PPC32::SRW, 2, DestReg+1).addReg(SrcReg+1).addReg(ShiftAmountReg);
- }
- }
+ BuildMI(*MBB, IP, PPC32::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
+ .addImm(32);
+ BuildMI(*MBB, IP, PPC32::SLW, 2, TmpReg2).addReg(SrcReg+1)
+ .addReg(ShiftAmountReg);
+ BuildMI(*MBB, IP, PPC32::SRW, 2,TmpReg3).addReg(SrcReg).addReg(TmpReg1);
+ BuildMI(*MBB, IP, PPC32::OR, 2,TmpReg4).addReg(TmpReg2).addReg(TmpReg3);
+ BuildMI(*MBB, IP, PPC32::ADDI, 2, TmpReg5).addReg(ShiftAmountReg)
+ .addImm(-32);
+ BuildMI(*MBB, IP, PPC32::SLW, 2,TmpReg6).addReg(SrcReg).addReg(TmpReg5);
+ BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(TmpReg4)
+ .addReg(TmpReg6);
+ BuildMI(*MBB, IP, PPC32::SLW, 2, DestReg).addReg(SrcReg)
+ .addReg(ShiftAmountReg);
+ } else {
+ if (isSigned) {
+ // FIXME: Unimplemented
+ // Page C-3 of the PowerPC 32bit Programming Environments Manual
+ std::cerr << "Unimplemented: signed right shift\n";
+ abort();
+ } else {
+ BuildMI(*MBB, IP, PPC32::SUBFIC, 2, TmpReg1).addReg(ShiftAmountReg)
+ .addImm(32);
+ BuildMI(*MBB, IP, PPC32::SRW, 2, TmpReg2).addReg(SrcReg)
+ .addReg(ShiftAmountReg);
+ BuildMI(*MBB, IP, PPC32::SLW, 2, TmpReg3).addReg(SrcReg+1)
+ .addReg(TmpReg1);
+ BuildMI(*MBB, IP, PPC32::OR, 2, TmpReg4).addReg(TmpReg2)
+ .addReg(TmpReg3);
+ BuildMI(*MBB, IP, PPC32::ADDI, 2, TmpReg5).addReg(ShiftAmountReg)
+ .addImm(-32);
+ BuildMI(*MBB, IP, PPC32::SRW, 2, TmpReg6).addReg(SrcReg+1)
+ .addReg(TmpReg5);
+ BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(TmpReg4)
+ .addReg(TmpReg6);
+ BuildMI(*MBB, IP, PPC32::SRW, 2, DestReg+1).addReg(SrcReg+1)
+ .addReg(ShiftAmountReg);
+ }
+ }
}
return;
}
assert(CUI->getType() == Type::UByteTy && "Shift amount not a ubyte?");
unsigned Amount = CUI->getValue();
- if (isLeftShift) {
- BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg).addImm(Amount).addImm(0).addImm(31-Amount);
- } else {
- if (isSigned) {
- BuildMI(*MBB, IP, PPC32::SRAWI, 2, DestReg).addReg(SrcReg).addImm(Amount);
- } else {
- BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg).addImm(32-Amount).addImm(Amount).addImm(31);
- }
- }
+ if (isLeftShift) {
+ BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg)
+ .addImm(Amount).addImm(0).addImm(31-Amount);
+ } else {
+ if (isSigned) {
+ BuildMI(*MBB, IP, PPC32::SRAWI,2,DestReg).addReg(SrcReg).addImm(Amount);
+ } else {
+ BuildMI(*MBB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg)
+ .addImm(32-Amount).addImm(Amount).addImm(31);
+ }
+ }
} else { // The shift amount is non-constant.
unsigned ShiftAmountReg = getReg (ShiftAmount, MBB, IP);
- if (isLeftShift) {
- BuildMI(*MBB, IP, PPC32::SLW, 2, DestReg).addReg(SrcReg).addReg(ShiftAmountReg);
- } else {
- BuildMI(*MBB, IP, isSigned ? PPC32::SRAW : PPC32::SRW, 2, DestReg).addReg(SrcReg).addReg(ShiftAmountReg);
- }
+ if (isLeftShift) {
+ BuildMI(*MBB, IP, PPC32::SLW, 2, DestReg).addReg(SrcReg)
+ .addReg(ShiftAmountReg);
+ } else {
+ BuildMI(*MBB, IP, isSigned ? PPC32::SRAW : PPC32::SRW, 2, DestReg)
+ .addReg(SrcReg).addReg(ShiftAmountReg);
+ }
}
}
/// visitLoadInst - Implement LLVM load instructions
///
void ISel::visitLoadInst(LoadInst &I) {
- static const unsigned Opcodes[] = { PPC32::LBZ, PPC32::LHZ, PPC32::LWZ, PPC32::LFS };
+ static const unsigned Opcodes[] = {
+ PPC32::LBZ, PPC32::LHZ, PPC32::LWZ, PPC32::LFS
+ };
unsigned Class = getClassB(I.getType());
unsigned Opcode = Opcodes[Class];
if (I.getType() == Type::DoubleTy) Opcode = PPC32::LFD;
unsigned DestReg = getReg(I);
if (AllocaInst *AI = dyn_castFixedAlloca(I.getOperand(0))) {
- unsigned FI = getFixedSizedAllocaFI(AI);
+ unsigned FI = getFixedSizedAllocaFI(AI);
if (Class == cLong) {
- addFrameReference(BuildMI(BB, PPC32::LWZ, 2, DestReg), FI);
- addFrameReference(BuildMI(BB, PPC32::LWZ, 2, DestReg+1), FI, 4);
+ addFrameReference(BuildMI(BB, PPC32::LWZ, 2, DestReg), FI);
+ addFrameReference(BuildMI(BB, PPC32::LWZ, 2, DestReg+1), FI, 4);
} else {
- addFrameReference(BuildMI(BB, Opcode, 2, DestReg), FI);
- }
+ addFrameReference(BuildMI(BB, Opcode, 2, DestReg), FI);
+ }
} else {
- unsigned SrcAddrReg = getReg(I.getOperand(0));
+ unsigned SrcAddrReg = getReg(I.getOperand(0));
if (Class == cLong) {
BuildMI(BB, PPC32::LWZ, 2, DestReg).addImm(0).addReg(SrcAddrReg);
unsigned Class = getClassB(ValTy);
if (Class == cLong) {
- BuildMI(BB, PPC32::STW, 3).addReg(ValReg).addImm(0).addReg(AddressReg);
- BuildMI(BB, PPC32::STW, 3).addReg(ValReg+1).addImm(4).addReg(AddressReg);
+ BuildMI(BB, PPC32::STW, 3).addReg(ValReg).addImm(0).addReg(AddressReg);
+ BuildMI(BB, PPC32::STW, 3).addReg(ValReg+1).addImm(4).addReg(AddressReg);
return;
}
/// emitCastOperation - Common code shared between visitCastInst and constant
/// expression cast support.
///
-void ISel::emitCastOperation(MachineBasicBlock *BB,
+void ISel::emitCastOperation(MachineBasicBlock *MBB,
MachineBasicBlock::iterator IP,
Value *Src, const Type *DestTy,
unsigned DestReg) {
const Type *SrcTy = Src->getType();
unsigned SrcClass = getClassB(SrcTy);
unsigned DestClass = getClassB(DestTy);
- unsigned SrcReg = getReg(Src, BB, IP);
+ unsigned SrcReg = getReg(Src, MBB, IP);
// Implement casts to bool by using compare on the operand followed by set if
// not zero on the result.
if (DestTy == Type::BoolTy) {
switch (SrcClass) {
case cByte:
- case cShort:
+ case cShort:
case cInt: {
unsigned TmpReg = makeAnotherReg(Type::IntTy);
- BuildMI(*BB, IP, PPC32::ADDIC, 2, TmpReg).addReg(SrcReg).addImm(-1);
- BuildMI(*BB, IP, PPC32::SUBFE, 2, DestReg).addReg(TmpReg).addReg(SrcReg);
+ BuildMI(*MBB, IP, PPC32::ADDIC, 2, TmpReg).addReg(SrcReg).addImm(-1);
+ BuildMI(*MBB, IP, PPC32::SUBFE, 2, DestReg).addReg(TmpReg).addReg(SrcReg);
break;
}
case cLong: {
unsigned TmpReg = makeAnotherReg(Type::IntTy);
unsigned SrcReg2 = makeAnotherReg(Type::IntTy);
- BuildMI(*BB, IP, PPC32::OR, 2, SrcReg2).addReg(SrcReg).addReg(SrcReg+1);
- BuildMI(*BB, IP, PPC32::ADDIC, 2, TmpReg).addReg(SrcReg2).addImm(-1);
- BuildMI(*BB, IP, PPC32::SUBFE, 2, DestReg).addReg(TmpReg).addReg(SrcReg2);
+ BuildMI(*MBB, IP, PPC32::OR, 2, SrcReg2).addReg(SrcReg).addReg(SrcReg+1);
+ BuildMI(*MBB, IP, PPC32::ADDIC, 2, TmpReg).addReg(SrcReg2).addImm(-1);
+ BuildMI(*MBB, IP, PPC32::SUBFE, 2, DestReg).addReg(TmpReg).addReg(SrcReg2);
break;
}
- case cFP:
- // FIXME
- // Load -0.0
- // Compare
- // move to CR1
- // Negate -0.0
- // Compare
- // CROR
- // MFCR
- // Left-align
- // SRA ?
- break;
+ case cFP32:
+ case cFP64:
+ // FSEL perhaps?
+ std::cerr << "Cast fp-to-bool not implemented!";
+ abort();
}
return;
}
// Implement casts between values of the same type class (as determined by
// getClass) by using a register-to-register move.
if (SrcClass == DestClass) {
- if (SrcClass <= cInt) {
- BuildMI(*BB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
- } else if (SrcClass == cFP && SrcTy == DestTy) {
- BuildMI(*BB, IP, PPC32::FMR, 1, DestReg).addReg(SrcReg);
- } else if (SrcClass == cFP) {
- if (SrcTy == Type::FloatTy) { // float -> double
- assert(DestTy == Type::DoubleTy && "Unknown cFP member!");
- BuildMI(*BB, IP, PPC32::FMR, 1, DestReg).addReg(SrcReg);
- } else { // double -> float
- assert(SrcTy == Type::DoubleTy && DestTy == Type::FloatTy &&
- "Unknown cFP member!");
- BuildMI(*BB, IP, PPC32::FRSP, 1, DestReg).addReg(SrcReg);
- }
+ if (SrcClass <= cInt) {
+ BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+ } else if (SrcClass == cFP32 || SrcClass == cFP64) {
+ BuildMI(*MBB, IP, PPC32::FMR, 1, DestReg).addReg(SrcReg);
} else if (SrcClass == cLong) {
- BuildMI(*BB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
- BuildMI(*BB, IP, PPC32::OR, 2, DestReg+1).addReg(SrcReg+1).addReg(SrcReg+1);
+ BuildMI(*MBB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+ BuildMI(*MBB, IP, PPC32::OR, 2, DestReg+1).addReg(SrcReg+1)
+ .addReg(SrcReg+1);
} else {
assert(0 && "Cannot handle this type of cast instruction!");
abort();
}
return;
}
-
+
+ // Handle cast of Float -> Double
+ if (SrcClass == cFP32 && DestClass == cFP64) {
+ BuildMI(*MBB, IP, PPC32::FMR, 1, DestReg).addReg(SrcReg);
+ return;
+ }
+
+ // Handle cast of Double -> Float
+ if (SrcClass == cFP64 && DestClass == cFP32) {
+ BuildMI(*MBB, IP, PPC32::FRSP, 1, DestReg).addReg(SrcReg);
+ return;
+ }
+
// Handle cast of SMALLER int to LARGER int using a move with sign extension
// or zero extension, depending on whether the source type was signed.
if (SrcClass <= cInt && (DestClass <= cInt || DestClass == cLong) &&
bool isUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
if (SrcClass < cInt) {
if (isUnsigned) {
- unsigned shift = (SrcClass == cByte) ? 24 : 16;
- BuildMI(*BB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg).addZImm(0).addImm(shift).addImm(31);
+ unsigned shift = (SrcClass == cByte) ? 24 : 16;
+ BuildMI(*BB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg).addZImm(0)
+ .addImm(shift).addImm(31);
} else {
- BuildMI(*BB, IP, (SrcClass == cByte) ? PPC32::EXTSB : PPC32::EXTSH, 1, DestReg).addReg(SrcReg);
- }
- } else {
- BuildMI(*BB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
- }
+ BuildMI(*BB, IP, (SrcClass == cByte) ? PPC32::EXTSB : PPC32::EXTSH,
+ 1, DestReg).addReg(SrcReg);
+ }
+ } else {
+ BuildMI(*BB, IP, PPC32::OR, 2, DestReg).addReg(SrcReg).addReg(SrcReg);
+ }
if (isLong) { // Handle upper 32 bits as appropriate...
if (isUnsigned) // Zero out top bits...
- BuildMI(*BB, IP, PPC32::ADDI, 2, DestReg+1).addReg(PPC32::R0).addImm(0);
+ BuildMI(*BB, IP, PPC32::LI, 1, DestReg+1).addImm(0);
else // Sign extend bottom half...
BuildMI(*BB, IP, PPC32::SRAWI, 2, DestReg+1).addReg(DestReg).addImm(31);
}
if ((SrcClass <= cInt || SrcClass == cLong) && DestClass <= cInt
&& SrcClass > DestClass) {
bool isUnsigned = SrcTy->isUnsigned() || SrcTy == Type::BoolTy;
- if (isUnsigned) {
- unsigned shift = (SrcClass == cByte) ? 24 : 16;
- BuildMI(*BB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg).addZImm(0).addImm(shift).addImm(31);
- } else {
- BuildMI(*BB, IP, (SrcClass == cByte) ? PPC32::EXTSB : PPC32::EXTSH, 1, DestReg).addReg(SrcReg);
- }
+ if (isUnsigned) {
+ unsigned shift = (SrcClass == cByte) ? 24 : 16;
+ BuildMI(*BB, IP, PPC32::RLWINM, 4, DestReg).addReg(SrcReg).addZImm(0)
+ .addImm(shift).addImm(31);
+ } else {
+ BuildMI(*BB, IP, (SrcClass == cByte) ? PPC32::EXTSB : PPC32::EXTSH, 1,
+ DestReg).addReg(SrcReg);
+ }
return;
}
// Handle casts from integer to floating point now...
- if (DestClass == cFP) {
-
- // Emit a library call for long to float conversion
- if (SrcClass == cLong) {
- std::vector<ValueRecord> Args;
- Args.push_back(ValueRecord(SrcReg, SrcTy));
- MachineInstr *TheCall = BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("__floatdidf", true);
- doCall(ValueRecord(DestReg, DestTy), TheCall, Args);
- return;
- }
+ if (DestClass == cFP32 || DestClass == cFP64) {
- unsigned TmpReg = makeAnotherReg(Type::IntTy);
- switch (SrcTy->getPrimitiveID()) {
- case Type::BoolTyID:
- case Type::SByteTyID:
- BuildMI(*BB, IP, PPC32::EXTSB, 1, TmpReg).addReg(SrcReg);
- break;
- case Type::UByteTyID:
- BuildMI(*BB, IP, PPC32::RLWINM, 4, TmpReg).addReg(SrcReg).addZImm(0).addImm(24).addImm(31);
- break;
- case Type::ShortTyID:
- BuildMI(*BB, IP, PPC32::EXTSB, 1, TmpReg).addReg(SrcReg);
- break;
- case Type::UShortTyID:
- BuildMI(*BB, IP, PPC32::RLWINM, 4, TmpReg).addReg(SrcReg).addZImm(0).addImm(16).addImm(31);
- break;
- case Type::IntTyID:
- BuildMI(*BB, IP, PPC32::OR, 2, TmpReg).addReg(SrcReg).addReg(SrcReg);
- break;
- case Type::UIntTyID:
- BuildMI(*BB, IP, PPC32::OR, 2, TmpReg).addReg(SrcReg).addReg(SrcReg);
- break;
- default: // No promotion needed...
- break;
+ // Emit a library call for long to float conversion
+ if (SrcClass == cLong) {
+ std::vector<ValueRecord> Args;
+ Args.push_back(ValueRecord(SrcReg, SrcTy));
+ Function *floatFn = (DestClass == cFP32) ? __floatdisfFn : __floatdidfFn;
+ MachineInstr *TheCall =
+ BuildMI(PPC32::CALLpcrel, 1).addGlobalAddress(floatFn, true);
+ doCall(ValueRecord(DestReg, DestTy), TheCall, Args, false);
+ return;
}
+ // Make sure we're dealing with a full 32 bits
+ unsigned TmpReg = makeAnotherReg(Type::IntTy);
+ promote32(TmpReg, ValueRecord(SrcReg, SrcTy));
+
SrcReg = TmpReg;
-
+
// Spill the integer to memory and reload it from there.
- // Also spill room for a special conversion constant
- int ConstantFrameIndex =
+ // Also spill room for a special conversion constant
+ int ConstantFrameIndex =
F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
int ValueFrameIdx =
F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
- unsigned constantHi = makeAnotherReg(Type::IntTy);
- unsigned constantLo = makeAnotherReg(Type::IntTy);
- unsigned ConstF = makeAnotherReg(Type::DoubleTy);
- unsigned TempF = makeAnotherReg(Type::DoubleTy);
-
+ unsigned constantHi = makeAnotherReg(Type::IntTy);
+ unsigned constantLo = makeAnotherReg(Type::IntTy);
+ unsigned ConstF = makeAnotherReg(Type::DoubleTy);
+ unsigned TempF = makeAnotherReg(Type::DoubleTy);
+
if (!SrcTy->isSigned()) {
- BuildMI(*BB, IP, PPC32::ADDIS, 2, constantHi).addReg(PPC32::R0).addImm(0x4330);
- BuildMI(*BB, IP, PPC32::ADDI, 2, constantLo).addReg(PPC32::R0).addImm(0);
- addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi), ConstantFrameIndex);
- addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantLo), ConstantFrameIndex, 4);
- addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi), ValueFrameIdx);
- addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(SrcReg), ValueFrameIdx, 4);
- addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, ConstF), ConstantFrameIndex);
- addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, TempF), ValueFrameIdx);
- BuildMI(*BB, IP, PPC32::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
- } else {
- unsigned TempLo = makeAnotherReg(Type::IntTy);
- BuildMI(*BB, IP, PPC32::ADDIS, 2, constantHi).addReg(PPC32::R0).addImm(0x4330);
- BuildMI(*BB, IP, PPC32::ADDIS, 2, constantLo).addReg(PPC32::R0).addImm(0x8000);
- addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi), ConstantFrameIndex);
- addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantLo), ConstantFrameIndex, 4);
- addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi), ValueFrameIdx);
- BuildMI(*BB, IP, PPC32::XORIS, 2, TempLo).addReg(SrcReg).addImm(0x8000);
- addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(TempLo), ValueFrameIdx, 4);
- addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, ConstF), ConstantFrameIndex);
- addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, TempF), ValueFrameIdx);
- BuildMI(*BB, IP, PPC32::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
- }
+ BuildMI(*BB, IP, PPC32::LIS, 1, constantHi).addImm(0x4330);
+ BuildMI(*BB, IP, PPC32::LI, 1, constantLo).addImm(0);
+ addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi),
+ ConstantFrameIndex);
+ addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantLo),
+ ConstantFrameIndex, 4);
+ addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi),
+ ValueFrameIdx);
+ addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(SrcReg),
+ ValueFrameIdx, 4);
+ addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, ConstF),
+ ConstantFrameIndex);
+ addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, TempF), ValueFrameIdx);
+ BuildMI(*BB, IP, PPC32::FSUB, 2, DestReg).addReg(TempF).addReg(ConstF);
+ } else {
+ unsigned TempLo = makeAnotherReg(Type::IntTy);
+ BuildMI(*BB, IP, PPC32::LIS, 1, constantHi).addImm(0x4330);
+ BuildMI(*BB, IP, PPC32::LIS, 1, constantLo).addImm(0x8000);
+ addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi),
+ ConstantFrameIndex);
+ addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantLo),
+ ConstantFrameIndex, 4);
+ addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(constantHi),
+ ValueFrameIdx);
+ BuildMI(*BB, IP, PPC32::XORIS, 2, TempLo).addReg(SrcReg).addImm(0x8000);
+ addFrameReference(BuildMI(*BB, IP, PPC32::STW, 3).addReg(TempLo),
+ ValueFrameIdx, 4);
+ addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, ConstF),
+ ConstantFrameIndex);
+ addFrameReference(BuildMI(*BB, IP, PPC32::LFD, 2, TempF), ValueFrameIdx);
+ BuildMI(*BB, IP, PPC32::FSUB, 2, DestReg).addReg(TempF ).addReg(ConstF);
+ }
return;
}
// Handle casts from floating point to integer now...
- if (SrcClass == cFP) {
-
- // emit library call
- if (DestClass == cLong) {
- std::vector<ValueRecord> Args;
- Args.push_back(ValueRecord(SrcReg, SrcTy));
- MachineInstr *TheCall = BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("__fixdfdi", true);
- doCall(ValueRecord(DestReg, DestTy), TheCall, Args);
- return;
- }
+ if (SrcClass == cFP32 || SrcClass == cFP64) {
+ // emit library call
+ if (DestClass == cLong) {
+ std::vector<ValueRecord> Args;
+ Args.push_back(ValueRecord(SrcReg, SrcTy));
+ Function *floatFn = (DestClass == cFP32) ? __fixsfdiFn : __fixdfdiFn;
+ MachineInstr *TheCall =
+ BuildMI(PPC32::CALLpcrel, 1).addGlobalAddress(floatFn, true);
+ doCall(ValueRecord(DestReg, DestTy), TheCall, Args, false);
+ return;
+ }
int ValueFrameIdx =
- F->getFrameInfo()->CreateStackObject(Type::DoubleTy, TM.getTargetData());
-
- // load into 32 bit value, and then truncate as necessary
- // FIXME: This is wrong for unsigned dest types
- //if (DestTy->isSigned()) {
- unsigned TempReg = makeAnotherReg(Type::DoubleTy);
- BuildMI(*BB, IP, PPC32::FCTIWZ, 1, TempReg).addReg(SrcReg);
- addFrameReference(BuildMI(*BB, IP, PPC32::STFD, 3).addReg(TempReg), ValueFrameIdx);
- addFrameReference(BuildMI(*BB, IP, PPC32::LWZ, 2, DestReg), ValueFrameIdx+4);
- //} else {
- //}
-
- // FIXME: Truncate return value
+ F->getFrameInfo()->CreateStackObject(SrcTy, TM.getTargetData());
+
+ if (DestTy->isSigned()) {
+ unsigned LoadOp = (DestClass == cShort) ? PPC32::LHA : PPC32::LWZ;
+ unsigned TempReg = makeAnotherReg(Type::DoubleTy);
+
+ // Convert to integer in the FP reg and store it to a stack slot
+ BuildMI(*BB, IP, PPC32::FCTIWZ, 1, TempReg).addReg(SrcReg);
+ addFrameReference(BuildMI(*BB, IP, PPC32::STFD, 3)
+ .addReg(TempReg), ValueFrameIdx);
+
+ // There is no load signed byte opcode, so we must emit a sign extend
+ if (DestClass == cByte) {
+ unsigned TempReg2 = makeAnotherReg(DestTy);
+ addFrameReference(BuildMI(*BB, IP, LoadOp, 2, TempReg2),
+ ValueFrameIdx, 4);
+ BuildMI(*MBB, IP, PPC32::EXTSB, DestReg).addReg(TempReg2);
+ } else {
+ addFrameReference(BuildMI(*BB, IP, LoadOp, 2, DestReg),
+ ValueFrameIdx, 4);
+ }
+ } else {
+ std::cerr << "Cast fp-to-unsigned not implemented!";
+ abort();
+ }
return;
}
unsigned DestReg = getReg(I);
unsigned Size;
- switch (I.getArgType()->getPrimitiveID()) {
+ switch (I.getArgType()->getTypeID()) {
default:
std::cerr << I;
assert(0 && "Error: bad type for va_next instruction!");
unsigned VAList = getReg(I.getOperand(0));
unsigned DestReg = getReg(I);
- switch (I.getType()->getPrimitiveID()) {
+ switch (I.getType()->getTypeID()) {
default:
std::cerr << I;
assert(0 && "Error: bad type for va_next instruction!");
///
void ISel::visitGetElementPtrInst(GetElementPtrInst &I) {
unsigned outputReg = getReg(I);
- emitGEPOperation(BB, BB->end(), I.getOperand(0),I.op_begin()+1, I.op_end(), outputReg);
+ emitGEPOperation(BB, BB->end(), I.getOperand(0), I.op_begin()+1, I.op_end(),
+ outputReg);
}
void ISel::emitGEPOperation(MachineBasicBlock *MBB,
Value *Src, User::op_iterator IdxBegin,
User::op_iterator IdxEnd, unsigned TargetReg) {
const TargetData &TD = TM.getTargetData();
- if (ConstantPointerRef *CPR = dyn_cast<ConstantPointerRef>(Src))
- Src = CPR->getValue();
std::vector<Value*> GEPOps;
GEPOps.resize(IdxEnd-IdxBegin+1);
// Keep emitting instructions until we consume the entire GEP instruction.
while (!GEPOps.empty()) {
+ if (GEPTypes.empty()) {
+ // Load the base pointer into a register.
+ unsigned Reg = getReg(Src, MBB, IP);
+ BuildMI(*MBB, IP, PPC32::OR, 2, TargetReg).addReg(Reg).addReg(Reg);
+ break; // we are now done
+ }
+ if (const StructType *StTy = dyn_cast<StructType>(GEPTypes.back())) {
+ // It's a struct access. CUI is the index into the structure,
+ // which names the field. This index must have unsigned type.
+ const ConstantUInt *CUI = cast<ConstantUInt>(GEPOps.back());
+
+ // Use the TargetData structure to pick out what the layout of the
+ // structure is in memory. Since the structure index must be constant, we
+ // can get its value and use it to find the right byte offset from the
+ // StructLayout class's list of structure member offsets.
+ unsigned Disp = TD.getStructLayout(StTy)->MemberOffsets[CUI->getValue()];
+ GEPOps.pop_back(); // Consume a GEP operand
+ GEPTypes.pop_back();
+ unsigned Reg = makeAnotherReg(Type::UIntTy);
+ unsigned DispReg = makeAnotherReg(Type::UIntTy);
+ BuildMI(*MBB, IP, PPC32::LI, 1, DispReg).addImm(Disp);
+ BuildMI(*MBB, IP, PPC32::ADD, 2, TargetReg).addReg(Reg).addReg(DispReg);
+ --IP; // Insert the next instruction before this one.
+ TargetReg = Reg; // Codegen the rest of the GEP into this
+ } else {
// It's an array or pointer access: [ArraySize x ElementType].
const SequentialType *SqTy = cast<SequentialType>(GEPTypes.back());
Value *idx = GEPOps.back();
GEPOps.pop_back(); // Consume a GEP operand
GEPTypes.pop_back();
-
+
// Many GEP instructions use a [cast (int/uint) to LongTy] as their
- // operand on X86. Handle this case directly now...
+ // operand. Handle this case directly now...
if (CastInst *CI = dyn_cast<CastInst>(idx))
if (CI->getOperand(0)->getType() == Type::IntTy ||
CI->getOperand(0)->getType() == Type::UIntTy)
idx = CI->getOperand(0);
-
+
// We want to add BaseReg to(idxReg * sizeof ElementType). First, we
// must find the size of the pointed-to type (Not coincidentally, the next
// type is the type of the elements in the array).
const Type *ElTy = SqTy->getElementType();
unsigned elementSize = TD.getTypeSize(ElTy);
-
- if (elementSize == 1) {
+
+ if (idx == Constant::getNullValue(idx->getType())) {
+ // GEP with idx 0 is a no-op
+ } else if (elementSize == 1) {
// If the element size is 1, we don't have to multiply, just add
unsigned idxReg = getReg(idx, MBB, IP);
unsigned Reg = makeAnotherReg(Type::UIntTy);
} else {
unsigned idxReg = getReg(idx, MBB, IP);
unsigned OffsetReg = makeAnotherReg(Type::UIntTy);
-
+
// Make sure we can back the iterator up to point to the first
// instruction emitted.
MachineBasicBlock::iterator BeforeIt = IP;
else
--BeforeIt;
doMultiplyConst(MBB, IP, OffsetReg, Type::IntTy, idxReg, elementSize);
-
+
// Emit an ADD to add OffsetReg to the basePtr.
unsigned Reg = makeAnotherReg(Type::UIntTy);
- BuildMI(*MBB, IP, PPC32::ADD, 2, TargetReg).addReg(Reg).addReg(OffsetReg);
+ BuildMI(*MBB, IP, PPC32::ADD,2,TargetReg).addReg(Reg).addReg(OffsetReg);
// Step to the first instruction of the multiply.
if (BeforeIt == MBB->end())
IP = MBB->begin();
else
IP = ++BeforeIt;
-
+
TargetReg = Reg; // Codegen the rest of the GEP into this
}
}
+ }
}
/// visitAllocaInst - If this is a fixed size alloca, allocate space from the
// AlignedSize = and <AddedSize>, ~15
unsigned AlignedSize = makeAnotherReg(Type::UIntTy);
- BuildMI(BB, PPC32::RLWNM, 4, AlignedSize).addReg(AddedSizeReg).addImm(0).addImm(0).addImm(27);
+ BuildMI(BB, PPC32::RLWNM, 4, AlignedSize).addReg(AddedSizeReg).addImm(0)
+ .addImm(0).addImm(27);
// Subtract size from stack pointer, thereby allocating some space.
BuildMI(BB, PPC32::SUB, 2, PPC32::R1).addReg(PPC32::R1).addReg(AlignedSize);
std::vector<ValueRecord> Args;
Args.push_back(ValueRecord(Arg, Type::UIntTy));
- MachineInstr *TheCall = BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("malloc", true);
- doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args);
+ MachineInstr *TheCall =
+ BuildMI(PPC32::CALLpcrel, 1).addGlobalAddress(mallocFn, true);
+ doCall(ValueRecord(getReg(I), I.getType()), TheCall, Args, false);
}
void ISel::visitFreeInst(FreeInst &I) {
std::vector<ValueRecord> Args;
Args.push_back(ValueRecord(I.getOperand(0)));
- MachineInstr *TheCall = BuildMI(PPC32::CALLpcrel, 1).addExternalSymbol("free", true);
- doCall(ValueRecord(0, Type::VoidTy), TheCall, Args);
+ MachineInstr *TheCall =
+ BuildMI(PPC32::CALLpcrel, 1).addGlobalAddress(freeFn, true);
+ doCall(ValueRecord(0, Type::VoidTy), TheCall, Args, false);
}
/// createPPC32SimpleInstructionSelector - This pass converts an LLVM function
projects / oota-llvm.git / blobdiff