Ok for vector_shuffle mask to contain undef elements.

[oota-llvm.git] / lib / Target / PowerPC / README.txt

diff --git a/lib/Target/PowerPC/README.txt b/lib/Target/PowerPC/README.txt
index 0024fabf86ac7868f66428eb85b1e7d9d76ef401..14a0bc124ed7f42bfa1374f323615426675535ef 100644 (file)
--- a/lib/Target/PowerPC/README.txt
+++ b/lib/Target/PowerPC/README.txt
@@ -1,3 +1,5 @@
+//===- README.txt - Notes for improving PowerPC-specific code gen ---------===//
+
 TODO:
 * gpr0 allocation
 * implement do-loop -> bdnz transform
@@ -10,41 +12,8 @@ still a codesize win.
 
 ===-------------------------------------------------------------------------===
 
-Should hint to the branch select pass that it doesn't need to print the second
-unconditional branch, so we don't end up with things like:
-       b .LBBl42__2E_expand_function_8_674     ; loopentry.24
-       b .LBBl42__2E_expand_function_8_42      ; NewDefault
-       b .LBBl42__2E_expand_function_8_42      ; NewDefault
-
-This occurs in SPASS.
-
-The power of diet coke came up with a solution to this today:
-
-We know the only two cases that can happen here are either:
-a) we have a conditional branch followed by a fallthrough to the next BB
-b) we have a conditional branch followed by an unconditional branch
-
-We also invented the BRTWOWAY node to model (b).
-
-Currently, these are modeled by the PPC_BRCOND node which is a 12-byte pseudo
-that codegens to 
-  bccinv false
-true:
-  b truebb
-false:
-  b falsebb 
-
-However, realizing that for (a), we can bccinv directly to the fallthrough 
-block, and for (b) we will already have another unconditional branch after
-the conditional branch (see SPASS case above), then we know that we don't need
-BRTWOWAY at all, and can just codegen PPC_BRCOND as 
-
-bccinv +8
-b truebb
-
-This will also allow us to selectively not run the ppc branch selector, by just
-selecting PPC_BRCOND pseudo directly to the correct conditional branch
-instruction for small functions.
+Teach the .td file to pattern match PPC::BR_COND to appropriate bc variant, so
+we don't have to always run the branch selector for small functions.
 
 ===-------------------------------------------------------------------------===
 
@@ -342,12 +311,6 @@ Generate lwbrx and other byteswapping load/store instructions when reasonable.
 
 ===-------------------------------------------------------------------------===
 
-Implement TargetConstantVec, and set up PPC to custom lower ConstantVec into
-TargetConstantVec's if it's one of the many forms that are algorithmically
-computable using the spiffy altivec instructions.
-
-===-------------------------------------------------------------------------===
-
 Compile this:
 
 int foo(int a) {
@@ -535,10 +498,6 @@ This theoretically may help improve twolf slightly (used in dimbox.c:142?).
 
 ===-------------------------------------------------------------------------===
 
-Implement PPCInstrInfo::isLoadFromStackSlot/isStoreToStackSlot for vector
-registers, to generate better spill code.
-
-===-------------------------------------------------------------------------===
 int foo(int N, int ***W, int **TK, int X) {
   int t, i;
   
@@ -551,5 +510,44 @@ int foo(int N, int ***W, int **TK, int X) {
 
 We generate relatively atrocious code for this loop compared to gcc.
 
+We could also strength reduce the rem and the div:
+http://www.lcs.mit.edu/pubs/pdf/MIT-LCS-TM-600.pdf
 
+===-------------------------------------------------------------------------===
+
+float foo(float X) { return (int)(X); }
+
+Currently produces:
+
+_foo:
+        fctiwz f0, f1
+        stfd f0, -8(r1)
+        lwz r2, -4(r1)
+        extsw r2, r2
+        std r2, -16(r1)
+        lfd f0, -16(r1)
+        fcfid f0, f0
+        frsp f1, f0
+        blr
+
+We could use a target dag combine to turn the lwz/extsw into an lwa when the 
+lwz has a single use.  Since LWA is cracked anyway, this would be a codesize
+win only.
+
+===-------------------------------------------------------------------------===
+
+We generate ugly code for this:
+
+void func(unsigned int *ret, float dx, float dy, float dz, float dw) {
+  unsigned code = 0;
+  if(dx < -dw) code |= 1;
+  if(dx > dw)  code |= 2;
+  if(dy < -dw) code |= 4;
+  if(dy > dw)  code |= 8;
+  if(dz < -dw) code |= 16;
+  if(dz > dw)  code |= 32;
+  *ret = code;
+}
+
+===-------------------------------------------------------------------------===