Add two new calling conventions for runtime calls

[oota-llvm.git] / lib / Target / R600 / AMDGPU.td

diff --git a/lib/Target/R600/AMDGPU.td b/lib/Target/R600/AMDGPU.td
index 099a4918474443d3b2e1d2ecbac14f2c4a1dddee..36c415609152dd8ef6fa8c0d7db7b375be4d2674 100644 (file)
--- a/lib/Target/R600/AMDGPU.td
+++ b/lib/Target/R600/AMDGPU.td
@@ -14,56 +14,39 @@ include "AMDILBase.td"
 // Subtarget Features
 //===----------------------------------------------------------------------===//
 
+// Debugging Features
+
+def FeatureDumpCode : SubtargetFeature <"DumpCode",
+        "DumpCode",
+        "true",
+        "Dump MachineInstrs in the CodeEmitter">;
+
+def FeatureIRStructurizer : SubtargetFeature <"disable-irstructurizer",
+        "EnableIRStructurizer",
+        "false",
+        "Disable IR Structurizer">;
+
+// Target features
+
+def FeatureIfCvt : SubtargetFeature <"disable-ifcvt",
+        "EnableIfCvt",
+        "false",
+        "Disable the if conversion pass">;
+
 def FeatureFP64     : SubtargetFeature<"fp64",
-        "CapsOverride[AMDGPUDeviceInfo::DoubleOps]",
+        "FP64",
         "true",
         "Enable 64bit double precision operations">;
-def FeatureByteAddress    : SubtargetFeature<"byte_addressable_store",
-        "CapsOverride[AMDGPUDeviceInfo::ByteStores]",
-        "true",
-        "Enable byte addressable stores">;
-def FeatureBarrierDetect : SubtargetFeature<"barrier_detect",
-        "CapsOverride[AMDGPUDeviceInfo::BarrierDetect]",
-        "true",
-        "Enable duplicate barrier detection(HD5XXX or later).">;
-def FeatureImages : SubtargetFeature<"images",
-        "CapsOverride[AMDGPUDeviceInfo::Images]",
-        "true",
-        "Enable image functions">;
-def FeatureMultiUAV : SubtargetFeature<"multi_uav",
-        "CapsOverride[AMDGPUDeviceInfo::MultiUAV]",
-        "true",
-        "Generate multiple UAV code(HD5XXX family or later)">;
-def FeatureMacroDB : SubtargetFeature<"macrodb",
-        "CapsOverride[AMDGPUDeviceInfo::MacroDB]",
-        "true",
-        "Use internal macrodb, instead of macrodb in driver">;
-def FeatureNoAlias : SubtargetFeature<"noalias",
-        "CapsOverride[AMDGPUDeviceInfo::NoAlias]",
-        "true",
-        "assert that all kernel argument pointers are not aliased">;
-def FeatureNoInline : SubtargetFeature<"no-inline",
-        "CapsOverride[AMDGPUDeviceInfo::NoInline]",
-        "true",
-        "specify whether to not inline functions">;
 
 def Feature64BitPtr : SubtargetFeature<"64BitPtr",
         "Is64bit",
-        "false",
+        "true",
         "Specify if 64bit addressing should be used.">;
 
 def Feature32on64BitPtr : SubtargetFeature<"64on32BitPtr",
         "Is32on64bit",
         "false",
         "Specify if 64bit sized pointers with 32bit addressing should be used.">;
-def FeatureDebug : SubtargetFeature<"debug",
-        "CapsOverride[AMDGPUDeviceInfo::Debug]",
-        "true",
-        "Debug mode is enabled, so disable hardware accelerated address spaces.">;
-def FeatureDumpCode : SubtargetFeature <"DumpCode",
-        "DumpCode",
-        "true",
-        "Dump MachineInstrs in the CodeEmitter">;
 
 def FeatureR600ALUInst : SubtargetFeature<"R600ALUInst",
         "R600ALUInst",
@@ -75,6 +58,11 @@ def FeatureVertexCache : SubtargetFeature<"HasVertexCache",
         "true",
         "Specify use of dedicated vertex cache.">;
 
+def FeatureCaymanISA : SubtargetFeature<"caymanISA",
+        "CaymanISA",
+        "true",
+        "Use Cayman ISA">;
+
 class SubtargetFeatureFetchLimit <string Value> :
                           SubtargetFeature <"fetch"#Value,
         "TexVTXClauseSize",
@@ -84,25 +72,37 @@ class SubtargetFeatureFetchLimit <string Value> :
 def FeatureFetchLimit8 : SubtargetFeatureFetchLimit <"8">;
 def FeatureFetchLimit16 : SubtargetFeatureFetchLimit <"16">;
 
+class SubtargetFeatureGeneration <string Value,
+                                  list<SubtargetFeature> Implies> :
+        SubtargetFeature <Value, "Gen", "AMDGPUSubtarget::"#Value,
+                          Value#" GPU generation", Implies>;
+
+def FeatureR600 : SubtargetFeatureGeneration<"R600",
+        [FeatureR600ALUInst, FeatureFetchLimit8]>;
+
+def FeatureR700 : SubtargetFeatureGeneration<"R700",
+        [FeatureFetchLimit16]>;
+
+def FeatureEvergreen : SubtargetFeatureGeneration<"EVERGREEN",
+        [FeatureFetchLimit16]>;
+
+def FeatureNorthernIslands : SubtargetFeatureGeneration<"NORTHERN_ISLANDS",
+        [FeatureFetchLimit16]>;
+
+def FeatureSouthernIslands : SubtargetFeatureGeneration<"SOUTHERN_ISLANDS",
+        [Feature64BitPtr, FeatureFP64]>;
+
+def FeatureSeaIslands : SubtargetFeatureGeneration<"SEA_ISLANDS",
+        [Feature64BitPtr, FeatureFP64]>;
 //===----------------------------------------------------------------------===//
 
 def AMDGPUInstrInfo : InstrInfo {
   let guessInstructionProperties = 1;
 }
 
-//===----------------------------------------------------------------------===//
-// Declare the target which we are implementing
-//===----------------------------------------------------------------------===//
-def AMDGPUAsmWriter : AsmWriter {
-    string AsmWriterClassName = "InstPrinter";
-    int Variant = 0;
-    bit isMCAsmWriter = 1;
-}
-
 def AMDGPU : Target {
   // Pull in Instruction Info:
   let InstructionSet = AMDGPUInstrInfo;
-  let AssemblyWriters = [AMDGPUAsmWriter];
 }
 
 // Include AMDGPU TD files