R600/SI: Add pattern for zero-extending i1 to i32

[oota-llvm.git] / lib / Target / R600 / AMDGPUAsmPrinter.cpp

diff --git a/lib/Target/R600/AMDGPUAsmPrinter.cpp b/lib/Target/R600/AMDGPUAsmPrinter.cpp
index 8aca57a6b4794cf7e896b8586476c2259dab6281..1ef3df3aedee86cd8e041210ce73a2f220cedf92 100644 (file)
--- a/lib/Target/R600/AMDGPUAsmPrinter.cpp
+++ b/lib/Target/R600/AMDGPUAsmPrinter.cpp
@@ -47,8 +47,7 @@ extern "C" void LLVMInitializeR600AsmPrinter() {
 
 AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
     : AsmPrinter(TM, Streamer) {
-  DisasmEnabled = TM.getSubtarget<AMDGPUSubtarget>().dumpCode() &&
-                  ! Streamer.hasRawTextSupport();
+  DisasmEnabled = TM.getSubtarget<AMDGPUSubtarget>().dumpCode();
 }
 
 /// We need to override this function so we can avoid
@@ -56,9 +55,7 @@ AMDGPUAsmPrinter::AMDGPUAsmPrinter(TargetMachine &TM, MCStreamer &Streamer)
 bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
   SetupMachineFunction(MF);
 
-  if (OutStreamer.hasRawTextSupport()) {
-    OutStreamer.EmitRawText("@" + MF.getName() + ":");
-  }
+  OutStreamer.emitRawComment(Twine('@') + MF.getName() + Twine(':'));
 
   MCContext &Context = getObjFileLowering().getContext();
   const MCSectionELF *ConfigSection = Context.getELFSection(".AMDGPU.config",
@@ -82,17 +79,24 @@ bool AMDGPUAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
   OutStreamer.SwitchSection(getObjFileLowering().getTextSection());
   EmitFunctionBody();
 
-  if (isVerbose() && OutStreamer.hasRawTextSupport()) {
+  if (isVerbose()) {
     const MCSectionELF *CommentSection
       = Context.getELFSection(".AMDGPU.csdata",
                               ELF::SHT_PROGBITS, 0,
                               SectionKind::getReadOnly());
     OutStreamer.SwitchSection(CommentSection);
 
-    OutStreamer.EmitRawText(
-      Twine("; Kernel info:\n") +
-      "; NumSgprs: " + Twine(KernelInfo.NumSGPR) + "\n" +
-      "; NumVgprs: " + Twine(KernelInfo.NumVGPR) + "\n");
+    if (STM.getGeneration() > AMDGPUSubtarget::NORTHERN_ISLANDS) {
+      OutStreamer.emitRawComment(" Kernel info:", false);
+      OutStreamer.emitRawComment(" NumSgprs: " + Twine(KernelInfo.NumSGPR),
+                                 false);
+      OutStreamer.emitRawComment(" NumVgprs: " + Twine(KernelInfo.NumVGPR),
+                                 false);
+    } else {
+      R600MachineFunctionInfo *MFI = MF.getInfo<R600MachineFunctionInfo>();
+      OutStreamer.emitRawComment(
+        Twine("SQ_PGM_RESOURCES:STACK_SIZE = " + Twine(MFI->StackSize)));
+    }
   }
 
   if (STM.dumpCode()) {
@@ -201,15 +205,13 @@ void AMDGPUAsmPrinter::findNumUsedRegistersSI(MachineFunction &MF,
       unsigned numOperands = MI.getNumOperands();
       for (unsigned op_idx = 0; op_idx < numOperands; op_idx++) {
         MachineOperand &MO = MI.getOperand(op_idx);
-        unsigned maxUsed;
         unsigned width = 0;
         bool isSGPR = false;
-        unsigned reg;
-        unsigned hwReg;
+
         if (!MO.isReg()) {
           continue;
         }
-        reg = MO.getReg();
+        unsigned reg = MO.getReg();
         if (reg == AMDGPU::VCC) {
           VCCUsed = true;
           continue;
@@ -259,8 +261,8 @@ void AMDGPUAsmPrinter::findNumUsedRegistersSI(MachineFunction &MF,
         } else {
           llvm_unreachable("Unknown register class");
         }
-        hwReg = RI->getEncodingValue(reg) & 0xff;
-        maxUsed = hwReg + width - 1;
+        unsigned hwReg = RI->getEncodingValue(reg) & 0xff;
+        unsigned maxUsed = hwReg + width - 1;
         if (isSGPR) {
           MaxSGPR = maxUsed > MaxSGPR ? maxUsed : MaxSGPR;
         } else {