//
//===----------------------------------------------------------------------===//
-#ifndef R600MACHINESCHEDULER_H_
-#define R600MACHINESCHEDULER_H_
+#ifndef LLVM_LIB_TARGET_R600_R600MACHINESCHEDULER_H
+#define LLVM_LIB_TARGET_R600_R600MACHINESCHEDULER_H
#include "R600InstrInfo.h"
+#include "llvm/ADT/PriorityQueue.h"
#include "llvm/CodeGen/MachineScheduler.h"
#include "llvm/Support/Debug.h"
-#include "llvm/ADT/PriorityQueue.h"
using namespace llvm;
namespace llvm {
-class CompareSUnit {
-public:
- bool operator()(const SUnit *S1, const SUnit *S2) {
- return S1->getDepth() > S2->getDepth();
- }
-};
-
class R600SchedStrategy : public MachineSchedStrategy {
- const ScheduleDAGMI *DAG;
+ const ScheduleDAGMILive *DAG;
const R600InstrInfo *TII;
const R600RegisterInfo *TRI;
MachineRegisterInfo *MRI;
- enum InstQueue {
- QAlu = 1,
- QFetch = 2,
- QOther = 4
- };
-
enum InstKind {
IDAlu,
IDFetch,
AluT_Z,
AluT_W,
AluT_XYZW,
+ AluPredX,
+ AluTrans,
AluDiscarded, // LLVM Instructions that are going to be eliminated
AluLast
};
- ReadyQueue *Available[IDLast], *Pending[IDLast];
- std::multiset<SUnit *, CompareSUnit> AvailableAlus[AluLast];
+ std::vector<SUnit *> Available[IDLast], Pending[IDLast];
+ std::vector<SUnit *> AvailableAlus[AluLast];
+ std::vector<SUnit *> PhysicalRegCopy;
InstKind CurInstKind;
int CurEmitted;
InstKind NextInstKind;
+ unsigned AluInstCount;
+ unsigned FetchInstCount;
+
int InstKindLimit[IDLast];
int OccupedSlotsMask;
public:
R600SchedStrategy() :
- DAG(0), TII(0), TRI(0), MRI(0) {
- Available[IDAlu] = new ReadyQueue(QAlu, "AAlu");
- Available[IDFetch] = new ReadyQueue(QFetch, "AFetch");
- Available[IDOther] = new ReadyQueue(QOther, "AOther");
- Pending[IDAlu] = new ReadyQueue(QAlu<<4, "PAlu");
- Pending[IDFetch] = new ReadyQueue(QFetch<<4, "PFetch");
- Pending[IDOther] = new ReadyQueue(QOther<<4, "POther");
+ DAG(nullptr), TII(nullptr), TRI(nullptr), MRI(nullptr) {
}
- virtual ~R600SchedStrategy() {
- for (unsigned I = 0; I < IDLast; ++I) {
- delete Available[I];
- delete Pending[I];
- }
- }
+ virtual ~R600SchedStrategy() {}
- virtual void initialize(ScheduleDAGMI *dag);
- virtual SUnit *pickNode(bool &IsTopNode);
- virtual void schedNode(SUnit *SU, bool IsTopNode);
- virtual void releaseTopNode(SUnit *SU);
- virtual void releaseBottomNode(SUnit *SU);
+ void initialize(ScheduleDAGMI *dag) override;
+ SUnit *pickNode(bool &IsTopNode) override;
+ void schedNode(SUnit *SU, bool IsTopNode) override;
+ void releaseTopNode(SUnit *SU) override;
+ void releaseBottomNode(SUnit *SU) override;
private:
std::vector<MachineInstr *> InstructionsGroupCandidate;
+ bool VLIW5;
int getInstKind(SUnit *SU);
bool regBelongsToClass(unsigned Reg, const TargetRegisterClass *RC) const;
AluKind getAluKind(SUnit *SU) const;
void LoadAlu();
- bool isAvailablesAluEmpty() const;
- SUnit *AttemptFillSlot (unsigned Slot);
+ unsigned AvailablesAluCount() const;
+ SUnit *AttemptFillSlot (unsigned Slot, bool AnyAlu);
void PrepareNextSlot();
- SUnit *PopInst(std::multiset<SUnit *, CompareSUnit> &Q);
+ SUnit *PopInst(std::vector<SUnit*> &Q, bool AnyALU);
void AssignSlot(MachineInstr *MI, unsigned Slot);
SUnit* pickAlu();
SUnit* pickOther(int QID);
- void MoveUnits(ReadyQueue *QSrc, ReadyQueue *QDst);
+ void MoveUnits(std::vector<SUnit *> &QSrc, std::vector<SUnit *> &QDst);
};
} // namespace llvm