public:
static char ID;
R600VectorRegMerger(TargetMachine &tm) : MachineFunctionPass(ID),
- TII (static_cast<const R600InstrInfo *>(tm.getInstrInfo())) { }
+ TII(0) { }
void getAnalysisUsage(AnalysisUsage &AU) const {
AU.setPreservesCFG();
const std::vector<std::pair<unsigned, unsigned> > &RemapChan,
unsigned Chan) {
for (unsigned j = 0, je = RemapChan.size(); j < je; j++) {
- if (RemapChan[j].first == Chan) {
+ if (RemapChan[j].first == Chan)
return RemapChan[j].second;
- break;
- }
}
llvm_unreachable("Chan wasn't reassigned");
}
std::vector<unsigned> UpdatedUndef = BaseRSI->UndefReg;
for (DenseMap<unsigned, unsigned>::iterator It = RSI->RegToChan.begin(),
E = RSI->RegToChan.end(); It != E; ++It) {
- if (BaseRSI->RegToChan.find((*It).first) != BaseRSI->RegToChan.end()) {
- UpdatedRegToChan[(*It).first] = (*It).second;
- continue;
- }
unsigned DstReg = MRI->createVirtualRegister(&AMDGPU::R600_Reg128RegClass);
unsigned SubReg = (*It).first;
unsigned Swizzle = (*It).second;
.addReg(SubReg)
.addImm(Chan);
UpdatedRegToChan[SubReg] = Chan;
- for (std::vector<unsigned>::iterator RemoveIt = UpdatedUndef.begin(),
- RemoveE = UpdatedUndef.end(); RemoveIt != RemoveE; ++ RemoveIt) {
- if (*RemoveIt == Chan)
- UpdatedUndef.erase(RemoveIt);
- }
+ std::vector<unsigned>::iterator ChanPos =
+ std::find(UpdatedUndef.begin(), UpdatedUndef.end(), Chan);
+ if (ChanPos != UpdatedUndef.end())
+ UpdatedUndef.erase(ChanPos);
+ assert(std::find(UpdatedUndef.begin(), UpdatedUndef.end(), Chan) ==
+ UpdatedUndef.end() &&
+ "UpdatedUndef shouldn't contain Chan more than once!");
DEBUG(dbgs() << " ->"; Tmp->dump(););
(void)Tmp;
SrcVec = DstReg;
}
bool R600VectorRegMerger::runOnMachineFunction(MachineFunction &Fn) {
+ TII = static_cast<const R600InstrInfo *>(Fn.getTarget().getInstrInfo());
MRI = &(Fn.getRegInfo());
for (MachineFunction::iterator MBB = Fn.begin(), MBBe = Fn.end();
MBB != MBBe; ++MBB) {
for (MachineBasicBlock::iterator MII = MB->begin(), MIIE = MB->end();
MII != MIIE; ++MII) {
MachineInstr *MI = MII;
- if (MI->getOpcode() != AMDGPU::REG_SEQUENCE)
+ if (MI->getOpcode() != AMDGPU::REG_SEQUENCE) {
+ if (TII->get(MI->getOpcode()).TSFlags & R600_InstFlag::TEX_INST) {
+ unsigned Reg = MI->getOperand(1).getReg();
+ for (MachineRegisterInfo::def_iterator It = MRI->def_begin(Reg),
+ E = MRI->def_end(); It != E; ++It) {
+ RemoveMI(&(*It));
+ }
+ }
continue;
+ }
+
RegSeqInfo RSI(*MRI, MI);