using namespace llvm;
-R600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm,
- const TargetInstrInfo &tii)
-: AMDGPURegisterInfo(tm, tii),
- TM(tm),
- TII(tii)
- { }
+R600RegisterInfo::R600RegisterInfo(AMDGPUTargetMachine &tm)
+: AMDGPURegisterInfo(tm),
+ TM(tm)
+ { RCW.RegWeight = 0; RCW.WeightLimit = 0;}
BitVector R600RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
BitVector Reserved(getNumRegs());
Reserved.set(*I);
}
- const R600InstrInfo *RII = static_cast<const R600InstrInfo*>(&TII);
+ for (TargetRegisterClass::iterator I = AMDGPU::TRegMemRegClass.begin(),
+ E = AMDGPU::TRegMemRegClass.end();
+ I != E; ++I) {
+ Reserved.set(*I);
+ }
+
+ const R600InstrInfo *RII =
+ static_cast<const R600InstrInfo*>(TM.getInstrInfo());
std::vector<unsigned> IndirectRegs = RII->getIndirectReservedRegs(MF);
for (std::vector<unsigned>::iterator I = IndirectRegs.begin(),
E = IndirectRegs.end();
unsigned R600RegisterInfo::getSubRegFromChannel(unsigned Channel) const {
switch (Channel) {
default: assert(!"Invalid channel index"); return 0;
- case 0: return AMDGPU::sel_x;
- case 1: return AMDGPU::sel_y;
- case 2: return AMDGPU::sel_z;
- case 3: return AMDGPU::sel_w;
+ case 0: return AMDGPU::sub0;
+ case 1: return AMDGPU::sub1;
+ case 2: return AMDGPU::sub2;
+ case 3: return AMDGPU::sub3;
}
}
+const RegClassWeight &R600RegisterInfo::getRegClassWeight(
+ const TargetRegisterClass *RC) const {
+ return RCW;
+}