//
//===----------------------------------------------------------------------===//
-#ifndef R600REGISTERINFO_H_
-#define R600REGISTERINFO_H_
+#ifndef LLVM_LIB_TARGET_R600_R600REGISTERINFO_H
+#define LLVM_LIB_TARGET_R600_R600REGISTERINFO_H
-#include "AMDGPUTargetMachine.h"
#include "AMDGPURegisterInfo.h"
namespace llvm {
-class R600TargetMachine;
-class TargetInstrInfo;
+class AMDGPUSubtarget;
struct R600RegisterInfo : public AMDGPURegisterInfo {
- AMDGPUTargetMachine &TM;
- const TargetInstrInfo &TII;
+ RegClassWeight RCW;
- R600RegisterInfo(AMDGPUTargetMachine &tm, const TargetInstrInfo &tii);
+ R600RegisterInfo(const AMDGPUSubtarget &st);
- virtual BitVector getReservedRegs(const MachineFunction &MF) const;
-
- /// \param RC is an AMDIL reg class.
- ///
- /// \returns the R600 reg class that is equivalent to \p RC.
- virtual const TargetRegisterClass *getISARegClass(
- const TargetRegisterClass *RC) const;
+ BitVector getReservedRegs(const MachineFunction &MF) const override;
/// \brief get the HW encoding for a register's channel.
unsigned getHWRegChan(unsigned reg) const;
+ unsigned getHWRegIndex(unsigned Reg) const override;
+
/// \brief get the register class of the specified type to use in the
/// CFGStructurizer
- virtual const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const;
+ const TargetRegisterClass * getCFGStructurizerRegClass(MVT VT) const override;
- /// \returns the sub reg enum value for the given \p Channel
- /// (e.g. getSubRegFromChannel(0) -> AMDGPU::sel_x)
- unsigned getSubRegFromChannel(unsigned Channel) const;
+ const RegClassWeight &
+ getRegClassWeight(const TargetRegisterClass *RC) const override;
+ // \returns true if \p Reg can be defined in one ALU caluse and used in another.
+ bool isPhysRegLiveAcrossClauses(unsigned Reg) const;
};
} // End namespace llvm
-#endif // AMDIDSAREGISTERINFO_H_
+#endif