Add two new calling conventions for runtime calls

[oota-llvm.git] / lib / Target / R600 / SIFixSGPRCopies.cpp

diff --git a/lib/Target/R600/SIFixSGPRCopies.cpp b/lib/Target/R600/SIFixSGPRCopies.cpp
index b518260700fd9a47c78a2032653d1b84a140523f..3370c7955bc75c56dadb0f9ea14953a4d29e762b 100644 (file)
--- a/lib/Target/R600/SIFixSGPRCopies.cpp
+++ b/lib/Target/R600/SIFixSGPRCopies.cpp
@@ -72,6 +72,7 @@
 #include "llvm/CodeGen/MachineInstrBuilder.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/Support/Debug.h"
+#include "llvm/Support/raw_ostream.h"
 #include "llvm/Target/TargetMachine.h"
 
 using namespace llvm;
@@ -180,16 +181,14 @@ bool SIFixSGPRCopies::isVGPRToSGPRCopy(const MachineInstr &Copy,
   unsigned SrcReg = Copy.getOperand(1).getReg();
   unsigned SrcSubReg = Copy.getOperand(1).getSubReg();
   const TargetRegisterClass *DstRC = MRI.getRegClass(DstReg);
+  const TargetRegisterClass *SrcRC;
 
   if (!TargetRegisterInfo::isVirtualRegister(SrcReg) ||
       DstRC == &AMDGPU::M0RegRegClass)
     return false;
 
-  const TargetRegisterClass *SrcRC = TRI->getSubRegClass(
-      MRI.getRegClass(SrcReg), SrcSubReg);
-
-  return TRI->isSGPRClass(DstRC) &&
-         !TRI->getCommonSubClass(DstRC, SrcRC);
+  SrcRC = inferRegClassFromDef(TRI, MRI, SrcReg, SrcSubReg);
+  return TRI->isSGPRClass(DstRC) && TRI->hasVGPRs(SrcRC);
 }
 
 bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
@@ -251,11 +250,10 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
             !hasVGPROperands(MI, TRI))
           continue;
 
-        DEBUG(dbgs() << "Fixing REG_SEQUENCE: \n");
+        DEBUG(dbgs() << "Fixing REG_SEQUENCE:\n");
         DEBUG(MI.print(dbgs()));
 
         TII->moveToVALU(MI);
-        TII->legalizeOperands(&MI);
         break;
       }
       }