SparcV9 doesnt have rem instruction either.

[oota-llvm.git] / lib / Target / R600 / SIFixSGPRCopies.cpp

diff --git a/lib/Target/R600/SIFixSGPRCopies.cpp b/lib/Target/R600/SIFixSGPRCopies.cpp
index 435172a08ee0d03f12b0e91582784270712b1836..7f07b01f087abebd993d88851ea99648dd64e284 100644 (file)
--- a/lib/Target/R600/SIFixSGPRCopies.cpp
+++ b/lib/Target/R600/SIFixSGPRCopies.cpp
@@ -143,7 +143,7 @@ bool SIFixSGPRCopies::runOnMachineFunction(MachineFunction &MF) {
       }
       unsigned Reg = MI.getOperand(0).getReg();
       const TargetRegisterClass *RC = inferRegClass(TRI, MRI, Reg);
-      if (RC == &AMDGPU::VSrc_32RegClass) {
+      if (TRI->getCommonSubClass(RC, &AMDGPU::VReg_32RegClass)) {
         MRI.constrainRegClass(Reg, &AMDGPU::VReg_32RegClass);
       }
     }