To-do
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-* Enable LSR for SPARC.
* Keep the address of the constant pool in a register instead of forming its
address all of the time.
* We can fold small constant offsets into the %hi/%lo references to constant
pool addresses as well.
* When in V9 mode, register allocate %icc[0-3].
+* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
* Emit the 'Branch on Integer Register with Prediction' instructions. It's
not clear how to write a pattern for this though:
1) should be replaced with a brz in V9 mode.
-* Same as above, but emit conditional move on register zero (p192) in V9
+* Same as above, but emit conditional move on register zero (p192) in V9
mode. Testcase:
int %t1(int %a, int %b) {
ret int %D
}
-* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
+* Emit MULX/[SU]DIVX instructions in V9 mode instead of fiddling
with the Y register, if they are faster.
* Codegen bswap(load)/store(bswap) -> load/store ASI
-* Implement frame pointer elimination, e.g. eliminate save/restore for
+* Implement frame pointer elimination, e.g. eliminate save/restore for
leaf fns.
* Fill delay slots
+* Implement JIT support
+
+* Use %g0 directly to materialize 0. No instruction is required.