The BLX instruction is encoded differently than the BL, because why not? In

[oota-llvm.git] / lib / Target / Sparc / README.txt

diff --git a/lib/Target/Sparc/README.txt b/lib/Target/Sparc/README.txt
index 352f842c21f4bca8856b2c34e9b86a4181a01f25..b4991fe5790b705e6dfa5a8e4bfc5aa351ded1ea 100644 (file)
--- a/lib/Target/Sparc/README.txt
+++ b/lib/Target/Sparc/README.txt
@@ -2,12 +2,12 @@
 To-do
 -----
 
-* Enable LSR for V8.
 * Keep the address of the constant pool in a register instead of forming its
   address all of the time.
 * We can fold small constant offsets into the %hi/%lo references to constant
   pool addresses as well.
 * When in V9 mode, register allocate %icc[0-3].
+* Add support for isel'ing UMUL_LOHI instead of marking it as Expand.
 * Emit the 'Branch on Integer Register with Prediction' instructions.  It's
   not clear how to write a pattern for this though:
 
@@ -56,3 +56,4 @@ int %t1(int %a, int %b) {
   leaf fns.
 * Fill delay slots
 
+* Implement JIT support