Adding dllimport, dllexport and external weak linkage types.

[oota-llvm.git] / lib / Target / Sparc / Sparc.td

diff --git a/lib/Target/Sparc/Sparc.td b/lib/Target/Sparc/Sparc.td
index 892b9cc350a4b419307e19960e3505293b57a4f1..1646e0e1f9649459fefd60bfef2ca6f8b2d5ff29 100644 (file)
--- a/lib/Target/Sparc/Sparc.td
+++ b/lib/Target/Sparc/Sparc.td
@@ -1,4 +1,4 @@
-//===- SparcV8.td - Describe the SparcV8 Target Machine ---------*- C++ -*-===//
+//===- Sparc.td - Describe the Sparc Target Machine -------------*- C++ -*-===//
 // 
 //                     The LLVM Compiler Infrastructure
 //
@@ -14,39 +14,67 @@
 // Target-independent interfaces which we are implementing
 //===----------------------------------------------------------------------===//
 
-include "../../Target.td"
+include "../Target.td"
+
+//===----------------------------------------------------------------------===//
+// SPARC Subtarget features.
+//
+ 
+def FeatureV9
+  : SubtargetFeature<"v9", "IsV9", "true",
+                     "Enable SPARC-V9 instructions">;
+def FeatureV8Deprecated
+  : SubtargetFeature<"deprecated-v8", "V8DeprecatedInsts", "true",
+                     "Enable deprecated V8 instructions in V9 mode">;
+def FeatureVIS
+  : SubtargetFeature<"vis", "IsVIS", "true",
+                     "Enable UltraSPARC Visual Instruction Set extensions">;
 
 //===----------------------------------------------------------------------===//
 // Register File Description
 //===----------------------------------------------------------------------===//
 
-include "SparcV8RegisterInfo.td"
+include "SparcRegisterInfo.td"
 
 //===----------------------------------------------------------------------===//
 // Instruction Descriptions
 //===----------------------------------------------------------------------===//
 
-include "SparcV8InstrInfo.td"
-
-def SparcV8InstrInfo : InstrInfo {
-  let PHIInst = PHI;
+include "SparcInstrInfo.td"
 
+def SparcInstrInfo : InstrInfo {
   // Define how we want to layout our target-specific information field.
   let TSFlagsFields = [];
   let TSFlagsShifts = [];
 }
 
 //===----------------------------------------------------------------------===//
-// Declare the target which we are implementing
+// SPARC processors supported.
 //===----------------------------------------------------------------------===//
 
-def SparcV8 : Target {
-  // Pointers are 32-bits in size.
-  let PointerType = i32;
+class Proc<string Name, list<SubtargetFeature> Features>
+ : Processor<Name, NoItineraries, Features>;
 
-  // FIXME: Specify callee-saved registers
-  let CalleeSavedRegisters = [];
+def : Proc<"generic",         []>;
+def : Proc<"v8",              []>;
+def : Proc<"supersparc",      []>;
+def : Proc<"sparclite",       []>;
+def : Proc<"f934",            []>;
+def : Proc<"hypersparc",      []>;
+def : Proc<"sparclite86x",    []>;
+def : Proc<"sparclet",        []>;
+def : Proc<"tsc701",          []>;
+def : Proc<"v9",              [FeatureV9]>;
+def : Proc<"ultrasparc",      [FeatureV9, FeatureV8Deprecated]>;
+def : Proc<"ultrasparc3",     [FeatureV9, FeatureV8Deprecated]>;
+def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
+
+
+//===----------------------------------------------------------------------===//
+// Declare the target which we are implementing
+//===----------------------------------------------------------------------===//
 
+def Sparc : Target {
   // Pull in Instruction Info:
-  let InstructionSet = SparcV8InstrInfo;
+  let InstructionSet = SparcInstrInfo;
 }