R600: Const/Neg/Abs can be folded to dot4

[oota-llvm.git] / lib / Target / Sparc / Sparc.td

diff --git a/lib/Target/Sparc/Sparc.td b/lib/Target/Sparc/Sparc.td
index b123930157d127aa47f7d0be074516ee8dfdf90b..d42c40faa15ae1bc18c22a0918a8035e60b9b28f 100644 (file)
--- a/lib/Target/Sparc/Sparc.td
+++ b/lib/Target/Sparc/Sparc.td
@@ -1,10 +1,10 @@
-//===- SparcV8.td - Describe the SparcV8 Target Machine ---------*- C++ -*-===//
-// 
+//===-- Sparc.td - Describe the Sparc Target Machine -------*- tablegen -*-===//
+//
 //                     The LLVM Compiler Infrastructure
 //
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
+//
 //===----------------------------------------------------------------------===//
 //
 //
@@ -14,12 +14,12 @@
 // Target-independent interfaces which we are implementing
 //===----------------------------------------------------------------------===//
 
-include "../Target.td"
+include "llvm/Target/Target.td"
 
 //===----------------------------------------------------------------------===//
 // SPARC Subtarget features.
 //
- 
+
 def FeatureV9
   : SubtargetFeature<"v9", "IsV9", "true",
                      "Enable SPARC-V9 instructions">;
@@ -31,22 +31,14 @@ def FeatureVIS
                      "Enable UltraSPARC Visual Instruction Set extensions">;
 
 //===----------------------------------------------------------------------===//
-// Register File Description
-//===----------------------------------------------------------------------===//
-
-include "SparcV8RegisterInfo.td"
-
-//===----------------------------------------------------------------------===//
-// Instruction Descriptions
+// Register File, Calling Conv, Instruction Descriptions
 //===----------------------------------------------------------------------===//
 
-include "SparcV8InstrInfo.td"
+include "SparcRegisterInfo.td"
+include "SparcCallingConv.td"
+include "SparcInstrInfo.td"
 
-def SparcV8InstrInfo : InstrInfo {
-  // Define how we want to layout our target-specific information field.
-  let TSFlagsFields = [];
-  let TSFlagsShifts = [];
-}
+def SparcInstrInfo : InstrInfo;
 
 //===----------------------------------------------------------------------===//
 // SPARC processors supported.
@@ -74,13 +66,7 @@ def : Proc<"ultrasparc3-vis", [FeatureV9, FeatureV8Deprecated, FeatureVIS]>;
 // Declare the target which we are implementing
 //===----------------------------------------------------------------------===//
 
-def SparcV8 : Target {
-  // Pointers are 32-bits in size.
-  let PointerType = i32;
-
-  // FIXME: Specify callee-saved registers
-  let CalleeSavedRegisters = [];
-
+def Sparc : Target {
   // Pull in Instruction Info:
-  let InstructionSet = SparcV8InstrInfo;
+  let InstructionSet = SparcInstrInfo;
 }