const SparcSubtarget &Subtarget;
public:
explicit SparcDAGToDAGISel(SparcTargetMachine &TM)
- : SelectionDAGISel(*TM.getTargetLowering()),
+ : SelectionDAGISel(TM),
Subtarget(TM.getSubtarget<SparcSubtarget>()) {
}
bool SelectADDRrr(SDValue Op, SDValue N, SDValue &R1, SDValue &R2);
bool SelectADDRri(SDValue Op, SDValue N, SDValue &Base,
SDValue &Offset);
-
+
+ /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
+ /// inline asm expressions.
+ virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+ char ConstraintCode,
+ std::vector<SDValue> &OutOps);
+
/// InstructionSelect - This callback is invoked by
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
virtual void InstructionSelect();
-
+
virtual const char *getPassName() const {
return "SPARC DAG->DAG Pattern Instruction Selection";
- }
-
+ }
+
// Include the pieces autogenerated from the target description.
#include "SparcGenDAGISel.inc"
};
/// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
void SparcDAGToDAGISel::InstructionSelect() {
DEBUG(BB->dump());
-
+
// Select target instructions for the DAG.
- SelectRoot();
+ SelectRoot(*CurDAG);
CurDAG->RemoveDeadNodes();
}
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress)
return false; // direct calls.
-
+
if (Addr.getOpcode() == ISD::ADD) {
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
if (Predicate_simm13(CN)) {
- if (FrameIndexSDNode *FIN =
+ if (FrameIndexSDNode *FIN =
dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
// Constant offset from frame ref.
Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
Addr.getOpcode() == ISD::TargetGlobalAddress)
return false; // direct calls.
-
+
if (Addr.getOpcode() == ISD::ADD) {
if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
Predicate_simm13(Addr.getOperand(1).getNode()))
// FIXME: should use a custom expander to expose the SRA to the dag.
SDValue DivLHS = N->getOperand(0);
SDValue DivRHS = N->getOperand(1);
- AddToISelQueue(DivLHS);
- AddToISelQueue(DivRHS);
-
+
// Set the Y register to the high-part.
SDValue TopPart;
if (N->getOpcode() == ISD::SDIV) {
unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
TopPart);
- }
+ }
case ISD::MULHU:
case ISD::MULHS: {
// FIXME: Handle mul by immediate.
SDValue MulLHS = N->getOperand(0);
SDValue MulRHS = N->getOperand(1);
- AddToISelQueue(MulLHS);
- AddToISelQueue(MulRHS);
unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
MulLHS, MulRHS);
return NULL;
}
}
-
+
return SelectCode(Op);
}
-/// createSparcISelDag - This pass converts a legalized DAG into a
+/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
+/// inline asm expressions.
+bool
+SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
+ char ConstraintCode,
+ std::vector<SDValue> &OutOps) {
+ SDValue Op0, Op1;
+ switch (ConstraintCode) {
+ default: return true;
+ case 'm': // memory
+ if (!SelectADDRrr(Op, Op, Op0, Op1))
+ SelectADDRri(Op, Op, Op0, Op1);
+ break;
+ }
+
+ OutOps.push_back(Op0);
+ OutOps.push_back(Op1);
+ return false;
+}
+
+/// createSparcISelDag - This pass converts a legalized DAG into a
/// SPARC-specific DAG, ready for instruction scheduling.
///
FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {