We need to propagate the debug location information even when dealing with the

[oota-llvm.git] / lib / Target / Sparc / SparcISelDAGToDAG.cpp

diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 64e9bcec6a181a225998bb6cc2932e32006ba7ad..c9bd62d0e20d69a1c0139379aa01f7bab7ccf325 100644 (file)
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -29,14 +29,12 @@ using namespace llvm;
 ///
 namespace {
 class SparcDAGToDAGISel : public SelectionDAGISel {
-  SparcTargetLowering Lowering;
-
   /// Subtarget - Keep a pointer to the Sparc Subtarget around so that we can
   /// make the right decision when generating code for different targets.
   const SparcSubtarget &Subtarget;
 public:
-  explicit SparcDAGToDAGISel(TargetMachine &TM)
-    : SelectionDAGISel(Lowering), Lowering(TM),
+  explicit SparcDAGToDAGISel(SparcTargetMachine &TM)
+    : SelectionDAGISel(TM),
       Subtarget(TM.getSubtarget<SparcSubtarget>()) {
   }
 
@@ -46,15 +44,21 @@ public:
   bool SelectADDRrr(SDValue Op, SDValue N, SDValue &R1, SDValue &R2);
   bool SelectADDRri(SDValue Op, SDValue N, SDValue &Base,
                     SDValue &Offset);
-  
+
+  /// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
+  /// inline asm expressions.
+  virtual bool SelectInlineAsmMemoryOperand(const SDValue &Op,
+                                            char ConstraintCode,
+                                            std::vector<SDValue> &OutOps);
+
   /// InstructionSelect - This callback is invoked by
   /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
   virtual void InstructionSelect();
-  
+
   virtual const char *getPassName() const {
     return "SPARC DAG->DAG Pattern Instruction Selection";
-  } 
-  
+  }
+
   // Include the pieces autogenerated from the target description.
 #include "SparcGenDAGISel.inc"
 };
@@ -64,9 +68,9 @@ public:
 /// SelectionDAGISel when it has created a SelectionDAG for us to codegen.
 void SparcDAGToDAGISel::InstructionSelect() {
   DEBUG(BB->dump());
-  
+
   // Select target instructions for the DAG.
-  SelectRoot();
+  SelectRoot(*CurDAG);
   CurDAG->RemoveDeadNodes();
 }
 
@@ -80,18 +84,18 @@ bool SparcDAGToDAGISel::SelectADDRri(SDValue Op, SDValue Addr,
   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
       Addr.getOpcode() == ISD::TargetGlobalAddress)
     return false;  // direct calls.
-  
+
   if (Addr.getOpcode() == ISD::ADD) {
     if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) {
       if (Predicate_simm13(CN)) {
-        if (FrameIndexSDNode *FIN = 
+        if (FrameIndexSDNode *FIN =
                 dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) {
           // Constant offset from frame ref.
           Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), MVT::i32);
         } else {
           Base = Addr.getOperand(0);
         }
-        Offset = CurDAG->getTargetConstant(CN->getValue(), MVT::i32);
+        Offset = CurDAG->getTargetConstant(CN->getZExtValue(), MVT::i32);
         return true;
       }
     }
@@ -117,10 +121,10 @@ bool SparcDAGToDAGISel::SelectADDRrr(SDValue Op, SDValue Addr,
   if (Addr.getOpcode() == ISD::TargetExternalSymbol ||
       Addr.getOpcode() == ISD::TargetGlobalAddress)
     return false;  // direct calls.
-  
+
   if (Addr.getOpcode() == ISD::ADD) {
     if (isa<ConstantSDNode>(Addr.getOperand(1)) &&
-        Predicate_simm13(Addr.getOperand(1).Val))
+        Predicate_simm13(Addr.getOperand(1).getNode()))
       return false;  // Let the reg+imm pattern catch this!
     if (Addr.getOperand(0).getOpcode() == SPISD::Lo ||
         Addr.getOperand(1).getOpcode() == SPISD::Lo)
@@ -136,7 +140,8 @@ bool SparcDAGToDAGISel::SelectADDRrr(SDValue Op, SDValue Addr,
 }
 
 SDNode *SparcDAGToDAGISel::Select(SDValue Op) {
-  SDNode *N = Op.Val;
+  SDNode *N = Op.getNode();
+  DebugLoc dl = N->getDebugLoc();
   if (N->isMachineOpcode())
     return NULL;   // Already selected.
 
@@ -147,48 +152,64 @@ SDNode *SparcDAGToDAGISel::Select(SDValue Op) {
     // FIXME: should use a custom expander to expose the SRA to the dag.
     SDValue DivLHS = N->getOperand(0);
     SDValue DivRHS = N->getOperand(1);
-    AddToISelQueue(DivLHS);
-    AddToISelQueue(DivRHS);
-    
+
     // Set the Y register to the high-part.
     SDValue TopPart;
     if (N->getOpcode() == ISD::SDIV) {
-      TopPart = SDValue(CurDAG->getTargetNode(SP::SRAri, MVT::i32, DivLHS,
+      TopPart = SDValue(CurDAG->getTargetNode(SP::SRAri, dl, MVT::i32, DivLHS,
                                    CurDAG->getTargetConstant(31, MVT::i32)), 0);
     } else {
       TopPart = CurDAG->getRegister(SP::G0, MVT::i32);
     }
-    TopPart = SDValue(CurDAG->getTargetNode(SP::WRYrr, MVT::Flag, TopPart,
+    TopPart = SDValue(CurDAG->getTargetNode(SP::WRYrr, dl, MVT::Flag, TopPart,
                                      CurDAG->getRegister(SP::G0, MVT::i32)), 0);
 
     // FIXME: Handle div by immediate.
     unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
     return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
                                 TopPart);
-  }    
+  }
   case ISD::MULHU:
   case ISD::MULHS: {
     // FIXME: Handle mul by immediate.
     SDValue MulLHS = N->getOperand(0);
     SDValue MulRHS = N->getOperand(1);
-    AddToISelQueue(MulLHS);
-    AddToISelQueue(MulRHS);
     unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
-    SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
+    SDNode *Mul = CurDAG->getTargetNode(Opcode, dl, MVT::i32, MVT::Flag,
                                         MulLHS, MulRHS);
     // The high part is in the Y register.
     return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDValue(Mul, 1));
     return NULL;
   }
   }
-  
+
   return SelectCode(Op);
 }
 
 
-/// createSparcISelDag - This pass converts a legalized DAG into a 
+/// SelectInlineAsmMemoryOperand - Implement addressing mode selection for
+/// inline asm expressions.
+bool
+SparcDAGToDAGISel::SelectInlineAsmMemoryOperand(const SDValue &Op,
+                                                char ConstraintCode,
+                                                std::vector<SDValue> &OutOps) {
+  SDValue Op0, Op1;
+  switch (ConstraintCode) {
+  default: return true;
+  case 'm':   // memory
+   if (!SelectADDRrr(Op, Op, Op0, Op1))
+     SelectADDRri(Op, Op, Op0, Op1);
+   break;
+  }
+
+  OutOps.push_back(Op0);
+  OutOps.push_back(Op1);
+  return false;
+}
+
+/// createSparcISelDag - This pass converts a legalized DAG into a
 /// SPARC-specific DAG, ready for instruction scheduling.
 ///
-FunctionPass *llvm::createSparcISelDag(TargetMachine &TM) {
+FunctionPass *llvm::createSparcISelDag(SparcTargetMachine &TM) {
   return new SparcDAGToDAGISel(TM);
 }