#include "llvm/Target/TargetLowering.h"
#include "llvm/Support/Debug.h"
#include <iostream>
+#include <queue>
#include <set>
using namespace llvm;
ITOF, // Int to FP within a FP register.
CALL, // A call instruction.
- RET_FLAG, // Return with a flag operand.
+ RET_FLAG // Return with a flag operand.
};
}
static SPCC::CondCodes FPCondCCodeToFCC(ISD::CondCode CC) {
switch (CC) {
default: assert(0 && "Unknown fp condition code!");
- case ISD::SETEQ: return SPCC::FCC_E;
- case ISD::SETNE: return SPCC::FCC_NE;
- case ISD::SETLT: return SPCC::FCC_L;
- case ISD::SETGT: return SPCC::FCC_G;
- case ISD::SETLE: return SPCC::FCC_LE;
- case ISD::SETGE: return SPCC::FCC_GE;
+ case ISD::SETEQ:
+ case ISD::SETOEQ: return SPCC::FCC_E;
+ case ISD::SETNE:
+ case ISD::SETUNE: return SPCC::FCC_NE;
+ case ISD::SETLT:
+ case ISD::SETOLT: return SPCC::FCC_L;
+ case ISD::SETGT:
+ case ISD::SETOGT: return SPCC::FCC_G;
+ case ISD::SETLE:
+ case ISD::SETOLE: return SPCC::FCC_LE;
+ case ISD::SETGE:
+ case ISD::SETOGE: return SPCC::FCC_GE;
case ISD::SETULT: return SPCC::FCC_UL;
case ISD::SETULE: return SPCC::FCC_ULE;
case ISD::SETUGT: return SPCC::FCC_UG;
addRegisterClass(MVT::f32, SP::FPRegsRegisterClass);
addRegisterClass(MVT::f64, SP::DFPRegsRegisterClass);
+ // Turn FP extload into load/fextend
+ setLoadXAction(ISD::EXTLOAD, MVT::f32, Expand);
+
// Custom legalize GlobalAddress nodes into LO/HI parts.
setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
setOperationAction(ISD::ConstantPool , MVT::i32, Custom);
setOperationAction(ISD::BIT_CONVERT, MVT::f32, Expand);
setOperationAction(ISD::BIT_CONVERT, MVT::i32, Expand);
- // Turn FP extload into load/fextend
- setOperationAction(ISD::EXTLOAD, MVT::f32, Expand);
-
// Sparc has no select or setcc: expand to SELECT_CC.
setOperationAction(ISD::SELECT, MVT::i32, Expand);
setOperationAction(ISD::SELECT, MVT::f32, Expand);
// Sparc doesn't have BRCOND either, it has BR_CC.
setOperationAction(ISD::BRCOND, MVT::Other, Expand);
+ setOperationAction(ISD::BRIND, MVT::Other, Expand);
+ setOperationAction(ISD::BR_JT, MVT::Other, Expand);
setOperationAction(ISD::BR_CC, MVT::i32, Custom);
setOperationAction(ISD::BR_CC, MVT::f32, Custom);
setOperationAction(ISD::BR_CC, MVT::f64, Custom);
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
SDOperand Load;
if (ObjectVT == MVT::i32) {
- Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
+ Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
} else {
- unsigned LoadOp =
+ ISD::LoadExtType LoadOp =
I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
// Sparc is big endian, so add an offset based on the ObjectVT.
FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
DAG.getConstant(Offset, MVT::i32));
Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
- DAG.getSrcValue(0), ObjectVT);
+ NULL, 0, ObjectVT);
Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
}
ArgValues.push_back(Load);
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
- SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, DAG.getSrcValue(0));
+ SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
ArgValues.push_back(Load);
}
ArgOffset += 4;
// because the double wouldn't be aligned!
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
- ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr,
- DAG.getSrcValue(0)));
+ ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0));
} else {
SDOperand HiVal;
if (CurArgReg < ArgRegEnd) { // Lives in an incoming GPR
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
- HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
+ HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
}
SDOperand LoVal;
} else {
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
- LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
+ LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
}
// Compose the two halves together into an i64 unit.
int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
- OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(),
- Arg, FIPtr, DAG.getSrcValue(0)));
+ OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0));
ArgOffset += 4;
}
}
if (!OutChains.empty())
- DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other, OutChains));
+ DAG.setRoot(DAG.getNode(ISD::TokenFactor, MVT::Other,
+ &OutChains[0], OutChains.size()));
// Finally, inform the code generator which regs we return values in.
switch (getValueType(F.getReturnType())) {
bool isVarArg, unsigned CC,
bool isTailCall, SDOperand Callee,
ArgListTy &Args, SelectionDAG &DAG) {
- MachineFunction &MF = DAG.getMachineFunction();
// Count the size of the outgoing arguments.
unsigned ArgsSize = 0;
for (unsigned i = 0, e = Args.size(); i != e; ++i) {
Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy()));
- SDOperand StackPtr, NullSV;
+ SDOperand StackPtr;
std::vector<SDOperand> Stores;
std::vector<SDOperand> RegValuesToPass;
unsigned ArgOffset = 68;
}
// Split the value into top and bottom part. Top part goes in a reg.
- SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
+ SDOperand Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
DAG.getConstant(1, MVT::i32));
- SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::i32, Val,
+ SDOperand Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, getPointerTy(), Val,
DAG.getConstant(0, MVT::i32));
RegValuesToPass.push_back(Hi);
if (ValToStore.Val) {
if (!StackPtr.Val) {
StackPtr = DAG.getRegister(SP::O6, MVT::i32);
- NullSV = DAG.getSrcValue(NULL);
}
SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
- Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
- ValToStore, PtrOff, NullSV));
+ Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
}
ArgOffset += ObjSize;
}
// Emit all stores, make sure the occur before any copies into physregs.
if (!Stores.empty())
- Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
+ Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size());
static const unsigned ArgRegs[] = {
SP::O0, SP::O1, SP::O2, SP::O3, SP::O4, SP::O5
std::vector<MVT::ValueType> NodeTys;
NodeTys.push_back(MVT::Other); // Returns a chain
NodeTys.push_back(MVT::Flag); // Returns a flag for retval copy to use.
- std::vector<SDOperand> Ops;
- Ops.push_back(Chain);
- Ops.push_back(Callee);
- if (InFlag.Val)
- Ops.push_back(InFlag);
- Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops);
+ SDOperand Ops[] = { Chain, Callee, InFlag };
+ Chain = DAG.getNode(SPISD::CALL, NodeTys, Ops, InFlag.Val ? 3 : 2);
InFlag = Chain.getValue(1);
MVT::ValueType RetTyVT = getValueType(RetTy);
return DAG.getNode(ISD::ADD, MVT::i32, Lo, Hi);
}
case ISD::ConstantPool: {
- Constant *C = cast<ConstantPoolSDNode>(Op)->get();
+ Constant *C = cast<ConstantPoolSDNode>(Op)->getConstVal();
SDOperand CP = DAG.getTargetConstantPool(C, MVT::i32,
cast<ConstantPoolSDNode>(Op)->getAlignment());
SDOperand Hi = DAG.getNode(SPISD::Hi, MVT::i32, CP);
std::vector<MVT::ValueType> VTs;
VTs.push_back(MVT::i32);
VTs.push_back(MVT::Flag);
- std::vector<SDOperand> Ops;
- Ops.push_back(LHS);
- Ops.push_back(RHS);
- CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1);
+ SDOperand Ops[2] = { LHS, RHS };
+ CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
Opc = SPISD::BRICC;
} else {
std::vector<MVT::ValueType> VTs;
VTs.push_back(LHS.getValueType()); // subcc returns a value
VTs.push_back(MVT::Flag);
- std::vector<SDOperand> Ops;
- Ops.push_back(LHS);
- Ops.push_back(RHS);
- CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops).getValue(1);
+ SDOperand Ops[2] = { LHS, RHS };
+ CompareFlag = DAG.getNode(SPISD::CMPICC, VTs, Ops, 2).getValue(1);
Opc = SPISD::SELECT_ICC;
if (SPCC == ~0U) SPCC = IntCondCCodeToICC(CC);
} else {
SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
DAG.getRegister(SP::I6, MVT::i32),
DAG.getConstant(VarArgsFrameOffset, MVT::i32));
- return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), Offset,
- Op.getOperand(1), Op.getOperand(2));
+ SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
+ return DAG.getStore(Op.getOperand(0), Offset,
+ Op.getOperand(1), SV->getValue(), SV->getOffset());
}
case ISD::VAARG: {
SDNode *Node = Op.Val;
MVT::ValueType VT = Node->getValueType(0);
SDOperand InChain = Node->getOperand(0);
SDOperand VAListPtr = Node->getOperand(1);
+ SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr,
- Node->getOperand(2));
+ SV->getValue(), SV->getOffset());
// Increment the pointer, VAList, to the next vaarg
SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList,
DAG.getConstant(MVT::getSizeInBits(VT)/8,
getPointerTy()));
// Store the incremented VAList to the legalized pointer
- InChain = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), NextPtr,
- VAListPtr, Node->getOperand(2));
+ InChain = DAG.getStore(VAList.getValue(1), NextPtr,
+ VAListPtr, SV->getValue(), SV->getOffset());
// Load the actual argument out of the pointer VAList, unless this is an
// f64 load.
if (VT != MVT::f64) {
- return DAG.getLoad(VT, InChain, VAList, DAG.getSrcValue(0));
+ return DAG.getLoad(VT, InChain, VAList, NULL, 0);
} else {
// Otherwise, load it as i64, then do a bitconvert.
- SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, DAG.getSrcValue(0));
+ SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
std::vector<MVT::ValueType> Tys;
Tys.push_back(MVT::f64);
Tys.push_back(MVT::Other);
- std::vector<SDOperand> Ops;
// Bit-Convert the value to f64.
- Ops.push_back(DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V));
- Ops.push_back(V.getValue(1));
- return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
+ SDOperand Ops[2] = { DAG.getNode(ISD::BIT_CONVERT, MVT::f64, V),
+ V.getValue(1) };
+ return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
}
}
case ISD::DYNAMIC_STACKALLOC: {
std::vector<MVT::ValueType> Tys;
Tys.push_back(MVT::i32);
Tys.push_back(MVT::Other);
- std::vector<SDOperand> Ops;
- Ops.push_back(NewVal);
- Ops.push_back(Chain);
- return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops);
+ SDOperand Ops[2] = { NewVal, Chain };
+ return DAG.getNode(ISD::MERGE_VALUES, Tys, Ops, 2);
}
case ISD::RET: {
SDOperand Copy;
abort();
case 1:
return SDOperand(); // ret void is legal
- case 2: {
+ case 3: {
unsigned ArgReg;
switch(Op.getOperand(1).getValueType()) {
default: assert(0 && "Unknown type to return!");
SDOperand());
break;
}
- case 3:
- Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(2),
+ case 5:
+ Copy = DAG.getCopyToReg(Op.getOperand(0), SP::I0, Op.getOperand(3),
SDOperand());
Copy = DAG.getCopyToReg(Copy, SP::I1, Op.getOperand(1), Copy.getValue(1));
break;
Subtarget(TM.getSubtarget<SparcSubtarget>()) {
}
- void Select(SDOperand &Result, SDOperand Op);
+ SDNode *Select(SDOperand Op);
// Complex Pattern Selectors.
bool SelectADDRrr(SDOperand N, SDOperand &R1, SDOperand &R2);
// Select target instructions for the DAG.
DAG.setRoot(SelectRoot(DAG.getRoot()));
- CodeGenMap.clear();
DAG.RemoveDeadNodes();
// Emit machine code to BB.
return true;
}
-void SparcDAGToDAGISel::Select(SDOperand &Result, SDOperand Op) {
+SDNode *SparcDAGToDAGISel::Select(SDOperand Op) {
SDNode *N = Op.Val;
if (N->getOpcode() >= ISD::BUILTIN_OP_END &&
- N->getOpcode() < SPISD::FIRST_NUMBER) {
- Result = Op;
- return; // Already selected.
- }
+ N->getOpcode() < SPISD::FIRST_NUMBER)
+ return NULL; // Already selected.
- // If this has already been converted, use it.
- std::map<SDOperand, SDOperand>::iterator CGMI = CodeGenMap.find(Op);
- if (CGMI != CodeGenMap.end()) {
- Result = CGMI->second;
- return;
- }
-
switch (N->getOpcode()) {
default: break;
case ISD::SDIV:
case ISD::UDIV: {
// FIXME: should use a custom expander to expose the SRA to the dag.
- SDOperand DivLHS, DivRHS;
- Select(DivLHS, N->getOperand(0));
- Select(DivRHS, N->getOperand(1));
+ SDOperand DivLHS = N->getOperand(0);
+ SDOperand DivRHS = N->getOperand(1);
+ AddToISelQueue(DivLHS);
+ AddToISelQueue(DivRHS);
// Set the Y register to the high-part.
SDOperand TopPart;
// FIXME: Handle div by immediate.
unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
- Result = CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS, TopPart);
- return;
+ return CurDAG->SelectNodeTo(N, Opcode, MVT::i32, DivLHS, DivRHS,
+ TopPart);
}
case ISD::MULHU:
case ISD::MULHS: {
// FIXME: Handle mul by immediate.
- SDOperand MulLHS, MulRHS;
- Select(MulLHS, N->getOperand(0));
- Select(MulRHS, N->getOperand(1));
+ SDOperand MulLHS = N->getOperand(0);
+ SDOperand MulRHS = N->getOperand(1);
+ AddToISelQueue(MulLHS);
+ AddToISelQueue(MulRHS);
unsigned Opcode = N->getOpcode() == ISD::MULHU ? SP::UMULrr : SP::SMULrr;
SDNode *Mul = CurDAG->getTargetNode(Opcode, MVT::i32, MVT::Flag,
MulLHS, MulRHS);
// The high part is in the Y register.
- Result = CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
- return;
+ return CurDAG->SelectNodeTo(N, SP::RDY, MVT::i32, SDOperand(Mul, 1));
+ return NULL;
}
}
- SelectCode(Result, Op);
+ return SelectCode(Op);
}