For PR786:

[oota-llvm.git] / lib / Target / Sparc / SparcISelDAGToDAG.cpp

diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 801cf4ec9bf4d498f608c12f2fc6530b3a124980..e6e036943bd3be9fa2606fde47f4b08b7336ff6c 100644 (file)
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -174,7 +174,8 @@ SparcTargetLowering::SparcTargetLowering(TargetMachine &TM)
   
   // Sparc doesn't have BRCOND either, it has BR_CC.
   setOperationAction(ISD::BRCOND, MVT::Other, Expand);
-  setOperationAction(ISD::BRIND, MVT::i32, Expand);
+  setOperationAction(ISD::BRIND, MVT::Other, Expand);
+  setOperationAction(ISD::BR_JT, MVT::Other, Expand);
   setOperationAction(ISD::BR_CC, MVT::i32, Custom);
   setOperationAction(ISD::BR_CC, MVT::f32, Custom);
   setOperationAction(ISD::BR_CC, MVT::f64, Custom);
@@ -330,7 +331,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
         SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
         SDOperand Load;
         if (ObjectVT == MVT::i32) {
-          Load = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
+          Load = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
         } else {
           ISD::LoadExtType LoadOp =
             I->getType()->isSigned() ? ISD::SEXTLOAD : ISD::ZEXTLOAD;
@@ -340,7 +341,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
           FIPtr = DAG.getNode(ISD::ADD, MVT::i32, FIPtr,
                               DAG.getConstant(Offset, MVT::i32));
           Load = DAG.getExtLoad(LoadOp, MVT::i32, Root, FIPtr,
-                                DAG.getSrcValue(0), ObjectVT);
+                                NULL, 0, ObjectVT);
           Load = DAG.getNode(ISD::TRUNCATE, ObjectVT, Load);
         }
         ArgValues.push_back(Load);
@@ -363,7 +364,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
       } else {
         int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
         SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
-        SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, DAG.getSrcValue(0));
+        SDOperand Load = DAG.getLoad(MVT::f32, Root, FIPtr, NULL, 0);
         ArgValues.push_back(Load);
       }
       ArgOffset += 4;
@@ -384,8 +385,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
         // because the double wouldn't be aligned!
         int FrameIdx = MF.getFrameInfo()->CreateFixedObject(8, ArgOffset);
         SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
-        ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, 
-                                        DAG.getSrcValue(0)));
+        ArgValues.push_back(DAG.getLoad(MVT::f64, Root, FIPtr, NULL, 0));
       } else {
         SDOperand HiVal;
         if (CurArgReg < ArgRegEnd) {  // Lives in an incoming GPR
@@ -395,7 +395,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
         } else {
           int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
           SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
-          HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
+          HiVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
         }
         
         SDOperand LoVal;
@@ -406,7 +406,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
         } else {
           int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset+4);
           SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
-          LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, DAG.getSrcValue(0));
+          LoVal = DAG.getLoad(MVT::i32, Root, FIPtr, NULL, 0);
         }
         
         // Compose the two halves together into an i64 unit.
@@ -437,8 +437,7 @@ SparcTargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
       int FrameIdx = MF.getFrameInfo()->CreateFixedObject(4, ArgOffset);
       SDOperand FIPtr = DAG.getFrameIndex(FrameIdx, MVT::i32);
 
-      OutChains.push_back(DAG.getNode(ISD::STORE, MVT::Other, DAG.getRoot(),
-                                      Arg, FIPtr, DAG.getSrcValue(0)));
+      OutChains.push_back(DAG.getStore(DAG.getRoot(), Arg, FIPtr, NULL, 0));
       ArgOffset += 4;
     }
   }
@@ -505,7 +504,7 @@ SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
 
   Chain = DAG.getCALLSEQ_START(Chain,DAG.getConstant(ArgsSize, getPointerTy()));
   
-  SDOperand StackPtr, NullSV;
+  SDOperand StackPtr;
   std::vector<SDOperand> Stores;
   std::vector<SDOperand> RegValuesToPass;
   unsigned ArgOffset = 68;
@@ -585,12 +584,10 @@ SparcTargetLowering::LowerCallTo(SDOperand Chain, const Type *RetTy,
     if (ValToStore.Val) {
       if (!StackPtr.Val) {
         StackPtr = DAG.getRegister(SP::O6, MVT::i32);
-        NullSV = DAG.getSrcValue(NULL);
       }
       SDOperand PtrOff = DAG.getConstant(ArgOffset, getPointerTy());
       PtrOff = DAG.getNode(ISD::ADD, MVT::i32, StackPtr, PtrOff);
-      Stores.push_back(DAG.getNode(ISD::STORE, MVT::Other, Chain,
-                                   ValToStore, PtrOff, NullSV));
+      Stores.push_back(DAG.getStore(Chain, ValToStore, PtrOff, NULL, 0));
     }
     ArgOffset += ObjSize;
   }
@@ -787,30 +784,32 @@ LowerOperation(SDOperand Op, SelectionDAG &DAG) {
     SDOperand Offset = DAG.getNode(ISD::ADD, MVT::i32,
                                    DAG.getRegister(SP::I6, MVT::i32),
                                 DAG.getConstant(VarArgsFrameOffset, MVT::i32));
-    return DAG.getNode(ISD::STORE, MVT::Other, Op.getOperand(0), Offset, 
-                       Op.getOperand(1), Op.getOperand(2));
+    SrcValueSDNode *SV = cast<SrcValueSDNode>(Op.getOperand(2));
+    return DAG.getStore(Op.getOperand(0), Offset, 
+                        Op.getOperand(1), SV->getValue(), SV->getOffset());
   }
   case ISD::VAARG: {
     SDNode *Node = Op.Val;
     MVT::ValueType VT = Node->getValueType(0);
     SDOperand InChain = Node->getOperand(0);
     SDOperand VAListPtr = Node->getOperand(1);
+    SrcValueSDNode *SV = cast<SrcValueSDNode>(Node->getOperand(2));
     SDOperand VAList = DAG.getLoad(getPointerTy(), InChain, VAListPtr,
-                                   Node->getOperand(2));
+                                   SV->getValue(), SV->getOffset());
     // Increment the pointer, VAList, to the next vaarg
     SDOperand NextPtr = DAG.getNode(ISD::ADD, getPointerTy(), VAList, 
                                     DAG.getConstant(MVT::getSizeInBits(VT)/8, 
                                                     getPointerTy()));
     // Store the incremented VAList to the legalized pointer
-    InChain = DAG.getNode(ISD::STORE, MVT::Other, VAList.getValue(1), NextPtr,
-                          VAListPtr, Node->getOperand(2));
+    InChain = DAG.getStore(VAList.getValue(1), NextPtr,
+                           VAListPtr, SV->getValue(), SV->getOffset());
     // Load the actual argument out of the pointer VAList, unless this is an
     // f64 load.
     if (VT != MVT::f64) {
-      return DAG.getLoad(VT, InChain, VAList, DAG.getSrcValue(0));
+      return DAG.getLoad(VT, InChain, VAList, NULL, 0);
     } else {
       // Otherwise, load it as i64, then do a bitconvert.
-      SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, DAG.getSrcValue(0));
+      SDOperand V = DAG.getLoad(MVT::i64, InChain, VAList, NULL, 0);
       std::vector<MVT::ValueType> Tys;
       Tys.push_back(MVT::f64);
       Tys.push_back(MVT::Other);