Fix an oversight: for modules with no other identifying target info,

[oota-llvm.git] / lib / Target / Sparc / SparcInstrInfo.cpp

diff --git a/lib/Target/Sparc/SparcInstrInfo.cpp b/lib/Target/Sparc/SparcInstrInfo.cpp
index 0a982fff31169541825b2bdb0859bb84cba53d61..a8c822ae9ae7070145f74f5cb2ac795b650c0d5f 100644 (file)
--- a/lib/Target/Sparc/SparcInstrInfo.cpp
+++ b/lib/Target/Sparc/SparcInstrInfo.cpp
@@ -19,7 +19,7 @@ using namespace llvm;
 
 SparcInstrInfo::SparcInstrInfo(SparcSubtarget &ST)
   : TargetInstrInfo(SparcInsts, sizeof(SparcInsts)/sizeof(SparcInsts[0])),
-    RI(ST) {
+    RI(ST, *this) {
 }
 
 static bool isZeroImm(const MachineOperand &op) {
@@ -97,10 +97,12 @@ unsigned SparcInstrInfo::isStoreToStackSlot(MachineInstr *MI,
   return 0;
 }
 
-void SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
-                                  MachineBasicBlock *FBB,
-                                  const std::vector<MachineOperand> &Cond)const{
+unsigned
+SparcInstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB,
+                             MachineBasicBlock *FBB,
+                             const std::vector<MachineOperand> &Cond)const{
   // Can only insert uncond branches so far.
   assert(Cond.empty() && !FBB && TBB && "Can only handle uncond branches!");
-  BuildMI(&MBB, SP::BA, 1).addMBB(TBB);
+  BuildMI(&MBB, get(SP::BA)).addMBB(TBB);
+  return 1;
 }