Refactoring of formal parameter flags. Enable properly use of

[oota-llvm.git] / lib / Target / Sparc / SparcInstrInfo.h

diff --git a/lib/Target/Sparc/SparcInstrInfo.h b/lib/Target/Sparc/SparcInstrInfo.h
index 9c7838dfdd7eefcfa39ad9beeb49acfa5495811e..9df9bad120566fd4acc36669c70a873070df70de 100644 (file)
--- a/lib/Target/Sparc/SparcInstrInfo.h
+++ b/lib/Target/Sparc/SparcInstrInfo.h
@@ -1,40 +1,40 @@
-//===- SparcV8InstrInfo.h - SparcV8 Instruction Information -----*- C++ -*-===//
-// 
+//===- SparcInstrInfo.h - Sparc Instruction Information ---------*- C++ -*-===//
+//
 //                     The LLVM Compiler Infrastructure
 //
 // This file was developed by the LLVM research group and is distributed under
 // the University of Illinois Open Source License. See LICENSE.TXT for details.
-// 
+//
 //===----------------------------------------------------------------------===//
 //
-// This file contains the SparcV8 implementation of the TargetInstrInfo class.
+// This file contains the Sparc implementation of the TargetInstrInfo class.
 //
 //===----------------------------------------------------------------------===//
 
-#ifndef SPARCV8INSTRUCTIONINFO_H
-#define SPARCV8INSTRUCTIONINFO_H
+#ifndef SPARCINSTRUCTIONINFO_H
+#define SPARCINSTRUCTIONINFO_H
 
 #include "llvm/Target/TargetInstrInfo.h"
-#include "SparcV8RegisterInfo.h"
+#include "SparcRegisterInfo.h"
 
 namespace llvm {
 
-/// V8II - This namespace holds all of the target specific flags that
+/// SPII - This namespace holds all of the target specific flags that
 /// instruction info tracks.
 ///
-namespace V8II {
+namespace SPII {
   enum {
     Pseudo = (1<<0),
     Load = (1<<1),
     Store = (1<<2),
     DelaySlot = (1<<3)
   };
-};
+}
 
-class SparcV8InstrInfo : public TargetInstrInfo {
-  const SparcV8RegisterInfo RI;
+class SparcInstrInfo : public TargetInstrInfo {
+  const SparcRegisterInfo RI;
 public:
-  SparcV8InstrInfo();
+  SparcInstrInfo(SparcSubtarget &ST);
 
   /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
   /// such, whenever a client has an instance of instruction info, it should
@@ -47,6 +47,25 @@ public:
   ///
   virtual bool isMoveInstr(const MachineInstr &MI,
                            unsigned &SrcReg, unsigned &DstReg) const;
+  
+  /// isLoadFromStackSlot - If the specified machine instruction is a direct
+  /// load from a stack slot, return the virtual or physical register number of
+  /// the destination along with the FrameIndex of the loaded stack slot.  If
+  /// not, return 0.  This predicate must return 0 if the instruction has
+  /// any side effects other than loading from the stack slot.
+  virtual unsigned isLoadFromStackSlot(MachineInstr *MI, int &FrameIndex) const;
+  
+  /// isStoreToStackSlot - If the specified machine instruction is a direct
+  /// store to a stack slot, return the virtual or physical register number of
+  /// the source reg along with the FrameIndex of the loaded stack slot.  If
+  /// not, return 0.  This predicate must return 0 if the instruction has
+  /// any side effects other than storing to the stack slot.
+  virtual unsigned isStoreToStackSlot(MachineInstr *MI, int &FrameIndex) const;
+  
+  
+  virtual void InsertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
+                            MachineBasicBlock *FBB,
+                            const std::vector<MachineOperand> &Cond) const;
 };
 
 }