Bools are *also* not ints. Sigh. Furthermore, most of the TargetMachine

[oota-llvm.git] / lib / Target / Sparc / SparcInstrInfo.td

diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td
index 84d63e692d3b5368c82250b7e82270d767b9d1bf..2bb5a5e3f0289a4fc7a0f566fd4a0c5e5d39ff84 100644 (file)
--- a/lib/Target/Sparc/SparcInstrInfo.td
+++ b/lib/Target/Sparc/SparcInstrInfo.td
@@ -100,12 +100,30 @@ let rd = 0, imm22 = 0 in
   def NOP : F2_1<0b100, "nop">;
 
 // Section B.11 - Logical Instructions, p. 106
-def ANDrr : F3_1<2, 0b000001, "and">;
-def ANDri : F3_2<2, 0b000001, "and">;
-def ORrr  : F3_1<2, 0b000010, "or">;
-def ORri  : F3_2<2, 0b000010, "or">;
-def XORrr : F3_1<2, 0b000011, "xor">;
-def XORri : F3_2<2, 0b000011, "xor">;
+def ANDrr   : F3_1<2, 0b000001, "and">;
+def ANDri   : F3_2<2, 0b000001, "and">;
+def ANDCCrr : F3_1<2, 0b010001, "andcc">;
+def ANDCCri : F3_2<2, 0b010001, "andcc">;
+def ANDNrr  : F3_1<2, 0b000101, "andn">;
+def ANDNri  : F3_2<2, 0b000101, "andn">;
+def ANDNCCrr: F3_1<2, 0b010101, "andncc">;
+def ANDNCCri: F3_2<2, 0b010101, "andncc">;
+def ORrr    : F3_1<2, 0b000010, "or">;
+def ORri    : F3_2<2, 0b000010, "or">;
+def ORCCrr  : F3_1<2, 0b010010, "orcc">;
+def ORCCri  : F3_2<2, 0b010010, "orcc">;
+def ORNrr   : F3_1<2, 0b000110, "orn">;
+def ORNri   : F3_2<2, 0b000110, "orn">;
+def ORNCCrr : F3_1<2, 0b010110, "orncc">;
+def ORNCCri : F3_2<2, 0b010110, "orncc">;
+def XORrr   : F3_1<2, 0b000011, "xor">;
+def XORri   : F3_2<2, 0b000011, "xor">;
+def XORCCrr : F3_1<2, 0b010011, "xorcc">;
+def XORCCri : F3_2<2, 0b010011, "xorcc">;
+def XNORrr  : F3_1<2, 0b000111, "xnor">;
+def XNORri  : F3_2<2, 0b000111, "xnor">;
+def XNORCCrr: F3_1<2, 0b010111, "xnorcc">;
+def XNORCCri: F3_2<2, 0b010111, "xnorcc">;
 
 // Section B.12 - Shift Instructions, p. 107
 def SLLrr : F3_1<2, 0b100101, "sll">;
@@ -136,8 +154,14 @@ def SUBXCCrr: F3_1<2, 0b011100, "subxcc">;
 def SUBXCCri: F3_2<2, 0b011100, "subxcc">;
 
 // Section B.18 - Multiply Instructions, p. 113
-def UMULrr : F3_1<2, 0b001010, "umul">;
-def SMULrr : F3_1<2, 0b001011, "smul">;
+def UMULrr  : F3_1<2, 0b001010, "umul">;
+def UMULri  : F3_2<2, 0b001010, "umul">;
+def SMULrr  : F3_1<2, 0b001011, "smul">;
+def SMULri  : F3_2<2, 0b001011, "smul">;
+def UMULCCrr: F3_1<2, 0b011010, "umulcc">;
+def UMULCCri: F3_2<2, 0b011010, "umulcc">;
+def SMULCCrr: F3_1<2, 0b011011, "smulcc">;
+def SMULCCri: F3_2<2, 0b011011, "smulcc">;
 
 // Section B.19 - Divide Instructions, p. 115
 def UDIVrr   : F3_1<2, 0b001110, "udiv">;