bit isPrivileged = 0; // Is this a privileged instruction?
}
-include "SparcV8InstrInfo_F2.td"
-include "SparcV8InstrInfo_F3.td"
+include "SparcV8InstrFormats.td"
//===----------------------------------------------------------------------===//
// Instructions
def ADJCALLSTACKUP : PseudoInstV8<"ADJCALLSTACKUP">;
def IMPLICIT_USE : PseudoInstV8<"IMPLICIT_USE">;
def IMPLICIT_DEF : PseudoInstV8<"IMPLICIT_DEF">;
+def FpMOVD : PseudoInstV8<"FpMOVD">; // pseudo 64-bit double move
// Section A.3 - Synthetic Instructions, p. 85
// special cases of JMPL:
-let isReturn = 1, isTerminator = 1, simm13 = 8 in
- def RET : F3_2<2, 0b111000, "ret">;
-let isReturn = 1, isTerminator = 1, simm13 = 8 in
- def RETL: F3_2<2, 0b111000, "retl">;
+let isReturn = 1, isTerminator = 1, hasDelaySlot = 1 in {
+ let rd = I7.Num, rs1 = G0.Num, simm13 = 8 in
+ def RET : F3_2<2, 0b111000, "ret">;
+ let rd = O7.Num, rs1 = G0.Num, simm13 = 8 in
+ def RETL: F3_2<2, 0b111000, "retl">;
+}
// CMP is a special case of SUBCC where destination is ignored, by setting it to
// %g0 (hardwired zero).
// FIXME: should keep track of the fact that it defs the integer condition codes
// Section B.10 - NOP Instruction, p. 105
// (It's a special case of SETHI)
-let rd = 0, imm = 0 in
+let rd = 0, imm22 = 0 in
def NOP : F2_1<0b100, "nop">;
// Section B.11 - Logical Instructions, p. 106
-def ANDrr : F3_1<2, 0b000001, "and">;
-def ANDri : F3_2<2, 0b000001, "and">;
-def ORrr : F3_1<2, 0b000010, "or">;
-def ORri : F3_2<2, 0b000010, "or">;
-def XORrr : F3_1<2, 0b000011, "xor">;
-def XORri : F3_2<2, 0b000011, "xor">;
+def ANDrr : F3_1<2, 0b000001, "and">;
+def ANDri : F3_2<2, 0b000001, "and">;
+def ANDCCrr : F3_1<2, 0b010001, "andcc">;
+def ANDCCri : F3_2<2, 0b010001, "andcc">;
+def ANDNrr : F3_1<2, 0b000101, "andn">;
+def ANDNri : F3_2<2, 0b000101, "andn">;
+def ANDNCCrr: F3_1<2, 0b010101, "andncc">;
+def ANDNCCri: F3_2<2, 0b010101, "andncc">;
+def ORrr : F3_1<2, 0b000010, "or">;
+def ORri : F3_2<2, 0b000010, "or">;
+def ORCCrr : F3_1<2, 0b010010, "orcc">;
+def ORCCri : F3_2<2, 0b010010, "orcc">;
+def ORNrr : F3_1<2, 0b000110, "orn">;
+def ORNri : F3_2<2, 0b000110, "orn">;
+def ORNCCrr : F3_1<2, 0b010110, "orncc">;
+def ORNCCri : F3_2<2, 0b010110, "orncc">;
+def XORrr : F3_1<2, 0b000011, "xor">;
+def XORri : F3_2<2, 0b000011, "xor">;
+def XORCCrr : F3_1<2, 0b010011, "xorcc">;
+def XORCCri : F3_2<2, 0b010011, "xorcc">;
+def XNORrr : F3_1<2, 0b000111, "xnor">;
+def XNORri : F3_2<2, 0b000111, "xnor">;
+def XNORCCrr: F3_1<2, 0b010111, "xnorcc">;
+def XNORCCri: F3_2<2, 0b010111, "xnorcc">;
// Section B.12 - Shift Instructions, p. 107
def SLLrr : F3_1<2, 0b100101, "sll">;
def SRAri : F3_2<2, 0b100111, "sra">;
// Section B.13 - Add Instructions, p. 108
-def ADDrr : F3_1<2, 0b000000, "add">;
-def ADDri : F3_2<2, 0b000000, "add">;
+def ADDrr : F3_1<2, 0b000000, "add">;
+def ADDri : F3_2<2, 0b000000, "add">;
+def ADDCCrr : F3_1<2, 0b010000, "addcc">;
+def ADDCCri : F3_2<2, 0b010000, "addcc">;
+def ADDXrr : F3_1<2, 0b001000, "addx">;
+def ADDXri : F3_2<2, 0b001000, "addx">;
+def ADDXCCrr: F3_1<2, 0b011000, "addxcc">;
+def ADDXCCri: F3_2<2, 0b011000, "addxcc">;
// Section B.15 - Subtract Instructions, p. 110
def SUBrr : F3_1<2, 0b000100, "sub">;
+def SUBri : F3_2<2, 0b000100, "sub">;
def SUBCCrr : F3_1<2, 0b010100, "subcc">;
def SUBCCri : F3_2<2, 0b010100, "subcc">;
+def SUBXrr : F3_1<2, 0b001100, "subx">;
+def SUBXri : F3_2<2, 0b001100, "subx">;
+def SUBXCCrr: F3_1<2, 0b011100, "subxcc">;
+def SUBXCCri: F3_2<2, 0b011100, "subxcc">;
// Section B.18 - Multiply Instructions, p. 113
-def UMULrr : F3_1<2, 0b001010, "umul">;
-def SMULrr : F3_1<2, 0b001011, "smul">;
+def UMULrr : F3_1<2, 0b001010, "umul">;
+def UMULri : F3_2<2, 0b001010, "umul">;
+def SMULrr : F3_1<2, 0b001011, "smul">;
+def SMULri : F3_2<2, 0b001011, "smul">;
+def UMULCCrr: F3_1<2, 0b011010, "umulcc">;
+def UMULCCri: F3_2<2, 0b011010, "umulcc">;
+def SMULCCrr: F3_1<2, 0b011011, "smulcc">;
+def SMULCCri: F3_2<2, 0b011011, "smulcc">;
// Section B.19 - Divide Instructions, p. 115
def UDIVrr : F3_1<2, 0b001110, "udiv">;
class BranchV8<bits<4> cc, string nm> : F2_2<cc, 0b010, nm> {
let isBranch = 1;
let isTerminator = 1;
+ let hasDelaySlot = 1;
}
-def BA : BranchV8<0b1000, "ba">;
+
+let isBarrier = 1 in
+ def BA : BranchV8<0b1000, "ba">;
def BN : BranchV8<0b0000, "bn">;
def BNE : BranchV8<0b1001, "bne">;
def BE : BranchV8<0b0001, "be">;
class FPBranchV8<bits<4> cc, string nm> : F2_2<cc, 0b110, nm> {
let isBranch = 1;
let isTerminator = 1;
+ let hasDelaySlot = 1;
}
def FBA : FPBranchV8<0b1000, "fba">;
def FBULE: FPBranchV8<0b1110, "fbule">;
def FBO : FPBranchV8<0b1111, "fbo">;
+
+
// Section B.24 - Call and Link Instruction, p. 125
// This is the only Format 1 instruction
-def CALL : InstV8 {
- bits<30> disp;
- let op = 1;
- let Inst{29-0} = disp;
- let Name = "call";
- let isCall = 1;
-}
-
-// Section B.25 - Jump and Link, p. 126
-let isCall = 1 in
+let Uses = [O0, O1, O2, O3, O4, O5], hasDelaySlot = 1, isCall = 1 in {
+ // pc-relative call:
+ let Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
+ D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
+ def CALL : InstV8 {
+ bits<30> disp;
+ let op = 1;
+ let Inst{29-0} = disp;
+ let Name = "call";
+ }
+
+ // indirect call (O7 is an EXPLICIT def in indirect calls, so it cannot also
+ // be an implicit def):
+ let Defs = [O0, O1, O2, O3, O4, O5, G1, G2, G3, G4, G5, G6, G7,
+ D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in
def JMPLrr : F3_1<2, 0b111000, "jmpl">; // jmpl [rs1+rs2], rd
+}
// Section B.29 - Write State Register Instructions
def WRrr : F3_1<2, 0b110000, "wr">; // wr rs1, rs2, rd
// Convert Integer to Floating-point Instructions, p. 141
def FITOS : F3_3<2, 0b110100, 0b011000100, "fitos">;
-def FITOD : F3_3<2, 0b110100, 0b011001000, "fitos">;
+def FITOD : F3_3<2, 0b110100, 0b011001000, "fitod">;
+
+// Convert Floating-point to Integer Instructions, p. 142
+def FSTOI : F3_3<2, 0b110100, 0b011010001, "fstoi">;
+def FDTOI : F3_3<2, 0b110100, 0b011010010, "fdtoi">;
// Convert between Floating-point Formats Instructions, p. 143
def FSTOD : F3_3<2, 0b110100, 0b011001001, "fstod">;
def FDIVD : F3_3<2, 0b110100, 0b001001110, "fdivd">;
// Floating-point Compare Instructions, p. 148
-// Note: the 2nd template arg is different for these guys
-def FCMPS : F3_3<2, 0b110101, 0b001010001, "fcmps">;
-def FCMPD : F3_3<2, 0b110101, 0b001010010, "fcmpd">;
-def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">;
-def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">;
+// Note: the 2nd template arg is different for these guys.
+// Note 2: the result of a FCMP is not available until the 2nd cycle
+// after the instr is retired, but there is no interlock. This behavior
+// is modelled as a delay slot.
+let hasDelaySlot = 1 in {
+ def FCMPS : F3_3<2, 0b110101, 0b001010001, "fcmps">;
+ def FCMPD : F3_3<2, 0b110101, 0b001010010, "fcmpd">;
+ def FCMPES : F3_3<2, 0b110101, 0b001010101, "fcmpes">;
+ def FCMPED : F3_3<2, 0b110101, 0b001010110, "fcmped">;
+}
projects / oota-llvm.git / blobdiff