//
// The LLVM Compiler Infrastructure
//
-// This file was developed by the LLVM research group and is distributed under
-// the University of Illinois Open Source License. See LICENSE.TXT for details.
+// This file is distributed under the University of Illinois Open Source
+// License. See LICENSE.TXT for details.
//
//===----------------------------------------------------------------------===//
//
def simm11 : PatLeaf<(imm), [{
// simm11 predicate - True if the imm fits in a 11-bit sign extended field.
- return (((int)N->getValue() << (32-11)) >> (32-11)) == (int)N->getValue();
+ return (((int)N->getZExtValue() << (32-11)) >> (32-11)) ==
+ (int)N->getZExtValue();
}]>;
def simm13 : PatLeaf<(imm), [{
// simm13 predicate - True if the imm fits in a 13-bit sign extended field.
- return (((int)N->getValue() << (32-13)) >> (32-13)) == (int)N->getValue();
+ return (((int)N->getZExtValue() << (32-13)) >> (32-13)) ==
+ (int)N->getZExtValue();
}]>;
def LO10 : SDNodeXForm<imm, [{
- return CurDAG->getTargetConstant((unsigned)N->getValue() & 1023, MVT::i32);
+ return CurDAG->getTargetConstant((unsigned)N->getZExtValue() & 1023,
+ MVT::i32);
}]>;
def HI22 : SDNodeXForm<imm, [{
// Transformation function: shift the immediate value down into the low bits.
- return CurDAG->getTargetConstant((unsigned)N->getValue() >> 10, MVT::i32);
+ return CurDAG->getTargetConstant((unsigned)N->getZExtValue() >> 10, MVT::i32);
}]>;
def SETHIimm : PatLeaf<(imm), [{
- return (((unsigned)N->getValue() >> 10) << 10) == (unsigned)N->getValue();
+ return (((unsigned)N->getZExtValue() >> 10) << 10) ==
+ (unsigned)N->getZExtValue();
}], HI22>;
// Addressing modes.
def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInFlag]>;
def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInFlag]>;
-// These are target-independent nodes, but have target-specific formats.
-def SDT_SPCallSeq_start : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
-def SDT_SPCallSeq_end : SDTypeProfile<0, 2, [ SDTCisVT<0, i32>,
- SDTCisVT<1, i32> ]>;
+// These are target-independent nodes, but have target-specific formats.
+def SDT_SPCallSeqStart : SDCallSeqStart<[ SDTCisVT<0, i32> ]>;
+def SDT_SPCallSeqEnd : SDCallSeqEnd<[ SDTCisVT<0, i32>,
+ SDTCisVT<1, i32> ]>;
-def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeq_start,
+def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeqStart,
[SDNPHasChain, SDNPOutFlag]>;
-def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeq_end,
+def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeqEnd,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
def call : SDNode<"SPISD::CALL", SDT_SPCall,
- [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
+ [SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
+
+def retflag : SDNode<"SPISD::RET_FLAG", SDTNone,
+ [SDNPHasChain, SDNPOptInFlag]>;
-def SDT_SPRetFlag : SDTypeProfile<0, 0, []>;
-def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRetFlag,
- [SDNPHasChain, SDNPOptInFlag]>;
+def getPCX : Operand<i32> {
+ let PrintMethod = "printGetPCX";
+}
//===----------------------------------------------------------------------===//
// SPARC Flag Conditions
class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
: InstSP<outs, ins, asmstr, pattern>;
+// GETPCX for PIC
+let Defs = [O7], Uses = [O7] in {
+ def GETPCX : Pseudo<(outs getPCX:$getpcseq), (ins), "$getpcseq", [] >;
+}
+
let Defs = [O6], Uses = [O6] in {
def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i32imm:$amt),
"!ADJCALLSTACKDOWN $amt",
- [(callseq_start imm:$amt)]>;
+ [(callseq_start timm:$amt)]>;
def ADJCALLSTACKUP : Pseudo<(outs), (ins i32imm:$amt1, i32imm:$amt2),
"!ADJCALLSTACKUP $amt1",
- [(callseq_end imm:$amt1, imm:$amt2)]>;
+ [(callseq_end timm:$amt1, timm:$amt2)]>;
}
-def IMPLICIT_DEF_Int : Pseudo<(outs IntRegs:$dst), (ins),
- "!IMPLICIT_DEF $dst",
- [(set IntRegs:$dst, (undef))]>;
-def IMPLICIT_DEF_FP : Pseudo<(outs FPRegs:$dst), (ins), "!IMPLICIT_DEF $dst",
- [(set FPRegs:$dst, (undef))]>;
-def IMPLICIT_DEF_DFP : Pseudo<(outs DFPRegs:$dst), (ins), "!IMPLICIT_DEF $dst",
- [(set DFPRegs:$dst, (undef))]>;
-
+
// FpMOVD/FpNEGD/FpABSD - These are lowered to single-precision ops by the
// fpmover pass.
let Predicates = [HasNoV9] in { // Only emit these in V8 mode.
(outs IntRegs:$dst), (ins MEMri:$addr),
"add ${addr:arith}, $dst",
[(set IntRegs:$dst, ADDRri:$addr)]>;
-
-defm ADDCC : F3_12<"addcc", 0b010000, addc>;
+
+let Defs = [ICC] in
+ defm ADDCC : F3_12<"addcc", 0b010000, addc>;
+
defm ADDX : F3_12<"addx", 0b001000, adde>;
// Section B.15 - Subtract Instructions, p. 110
defm SUB : F3_12 <"sub" , 0b000100, sub>;
defm SUBX : F3_12 <"subx" , 0b001100, sube>;
-defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>;
-def SUBXCCrr: F3_1<2, 0b011100,
- (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
- "subxcc $b, $c, $dst", []>;
+let Defs = [ICC] in {
+ defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>;
+
+ def SUBXCCrr: F3_1<2, 0b011100,
+ (outs IntRegs:$dst), (ins IntRegs:$b, IntRegs:$c),
+ "subxcc $b, $c, $dst", []>;
+}
// Section B.18 - Multiply Instructions, p. 113
defm UMUL : F3_12np<"umul", 0b001010>;
def BA : BranchSP<0b1000, (ins brtarget:$dst),
"ba $dst",
[(br bb:$dst)]>;
-
+
// FIXME: the encoding for the JIT should look at the condition field.
-def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc),
- "b$cc $dst",
- [(SPbricc bb:$dst, imm:$cc)]>;
+let Uses = [ICC] in
+ def BCOND : BranchSP<0, (ins brtarget:$dst, CCOp:$cc),
+ "b$cc $dst",
+ [(SPbricc bb:$dst, imm:$cc)]>;
// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
}
// FIXME: the encoding for the JIT should look at the condition field.
-def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc),
- "fb$cc $dst",
- [(SPbrfcc bb:$dst, imm:$cc)]>;
+let Uses = [FCC] in
+ def FBCOND : FPBranchSP<0, (ins brtarget:$dst, CCOp:$cc),
+ "fb$cc $dst",
+ [(SPbrfcc bb:$dst, imm:$cc)]>;
// Section B.24 - Call and Link Instruction, p. 125
// Note 2: the result of a FCMP is not available until the 2nd cycle
// after the instr is retired, but there is no interlock. This behavior
// is modelled with a forced noop after the instruction.
-def FCMPS : F3_3<2, 0b110101, 0b001010001,
- (outs), (ins FPRegs:$src1, FPRegs:$src2),
- "fcmps $src1, $src2\n\tnop",
- [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>;
-def FCMPD : F3_3<2, 0b110101, 0b001010010,
- (outs), (ins DFPRegs:$src1, DFPRegs:$src2),
- "fcmpd $src1, $src2\n\tnop",
- [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>;
-
+let Defs = [FCC] in {
+ def FCMPS : F3_3<2, 0b110101, 0b001010001,
+ (outs), (ins FPRegs:$src1, FPRegs:$src2),
+ "fcmps $src1, $src2\n\tnop",
+ [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>;
+ def FCMPD : F3_3<2, 0b110101, 0b001010010,
+ (outs), (ins DFPRegs:$src1, DFPRegs:$src2),
+ "fcmpd $src1, $src2\n\tnop",
+ [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>;
+}
//===----------------------------------------------------------------------===//
// V9 Instructions
def : Pat<(call texternalsym:$dst),
(CALL texternalsym:$dst)>;
-def : Pat<(ret), (RETL)>;
-
// Map integer extload's to zextloads.
def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
// zextload bool -> zextload byte
def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
-
-// truncstore bool -> truncstore byte.
-def : Pat<(truncstorei1 IntRegs:$src, ADDRrr:$addr),
- (STBrr ADDRrr:$addr, IntRegs:$src)>;
-def : Pat<(truncstorei1 IntRegs:$src, ADDRri:$addr),
- (STBri ADDRri:$addr, IntRegs:$src)>;