For PR786:

[oota-llvm.git] / lib / Target / Sparc / SparcInstrInfo.td

diff --git a/lib/Target/Sparc/SparcInstrInfo.td b/lib/Target/Sparc/SparcInstrInfo.td
index 0137a0d622468b13530075c68cc72315be7acf8f..6b7cddcdcb07a743dc08ee0551ab427d9789aa94 100644 (file)
--- a/lib/Target/Sparc/SparcInstrInfo.td
+++ b/lib/Target/Sparc/SparcInstrInfo.td
@@ -67,8 +67,8 @@ def SETHIimm : PatLeaf<(imm), [{
 }], HI22>;
 
 // Addressing modes.
-def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>;
-def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex]>;
+def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
+def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>;
 
 // Address operands
 def MEMrr : Operand<i32> {
@@ -205,10 +205,10 @@ class Pseudo<dag ops, string asmstr, list<dag> pattern>
 
 def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt),
                                "!ADJCALLSTACKDOWN $amt",
-                               [(callseq_start imm:$amt)]>;
+                               [(callseq_start imm:$amt)]>, Imp<[O6],[O6]>;
 def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt),
                             "!ADJCALLSTACKUP $amt",
-                            [(callseq_end imm:$amt)]>;
+                            [(callseq_end imm:$amt)]>, Imp<[O6],[O6]>;
 def IMPLICIT_DEF_Int : Pseudo<(ops IntRegs:$dst),
                               "!IMPLICIT_DEF $dst",
                               [(set IntRegs:$dst, (undef))]>;
@@ -278,35 +278,35 @@ let isReturn = 1, isTerminator = 1, hasDelaySlot = 1, noResults = 1 in {
 def LDSBrr : F3_1<3, 0b001001,
                   (ops IntRegs:$dst, MEMrr:$addr),
                   "ldsb [$addr], $dst",
-                  [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>;
+                  [(set IntRegs:$dst, (sextloadi8 ADDRrr:$addr))]>;
 def LDSBri : F3_2<3, 0b001001,
                   (ops IntRegs:$dst, MEMri:$addr),
                   "ldsb [$addr], $dst",
-                  [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>;
+                  [(set IntRegs:$dst, (sextloadi8 ADDRri:$addr))]>;
 def LDSHrr : F3_1<3, 0b001010,
                   (ops IntRegs:$dst, MEMrr:$addr),
                   "ldsh [$addr], $dst",
-                  [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>;
+                  [(set IntRegs:$dst, (sextloadi16 ADDRrr:$addr))]>;
 def LDSHri : F3_2<3, 0b001010,
                   (ops IntRegs:$dst, MEMri:$addr),
                   "ldsh [$addr], $dst",
-                  [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>;
+                  [(set IntRegs:$dst, (sextloadi16 ADDRri:$addr))]>;
 def LDUBrr : F3_1<3, 0b000001,
                   (ops IntRegs:$dst, MEMrr:$addr),
                   "ldub [$addr], $dst",
-                  [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>;
+                  [(set IntRegs:$dst, (zextloadi8 ADDRrr:$addr))]>;
 def LDUBri : F3_2<3, 0b000001,
                   (ops IntRegs:$dst, MEMri:$addr),
                   "ldub [$addr], $dst",
-                  [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>;
+                  [(set IntRegs:$dst, (zextloadi8 ADDRri:$addr))]>;
 def LDUHrr : F3_1<3, 0b000010,
                   (ops IntRegs:$dst, MEMrr:$addr),
                   "lduh [$addr], $dst",
-                  [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>;
+                  [(set IntRegs:$dst, (zextloadi16 ADDRrr:$addr))]>;
 def LDUHri : F3_2<3, 0b000010,
                   (ops IntRegs:$dst, MEMri:$addr),
                   "lduh [$addr], $dst",
-                  [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>;
+                  [(set IntRegs:$dst, (zextloadi16 ADDRri:$addr))]>;
 def LDrr   : F3_1<3, 0b000000,
                   (ops IntRegs:$dst, MEMrr:$addr),
                   "ld [$addr], $dst",
@@ -338,19 +338,19 @@ def LDDFri : F3_2<3, 0b100011,
 def STBrr : F3_1<3, 0b000101,
                  (ops MEMrr:$addr, IntRegs:$src),
                  "stb $src, [$addr]",
-                 [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>;
+                 [(truncstorei8 IntRegs:$src, ADDRrr:$addr)]>;
 def STBri : F3_2<3, 0b000101,
                  (ops MEMri:$addr, IntRegs:$src),
                  "stb $src, [$addr]",
-                 [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>;
+                 [(truncstorei8 IntRegs:$src, ADDRri:$addr)]>;
 def STHrr : F3_1<3, 0b000110,
                  (ops MEMrr:$addr, IntRegs:$src),
                  "sth $src, [$addr]",
-                 [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>;
+                 [(truncstorei16 IntRegs:$src, ADDRrr:$addr)]>;
 def STHri : F3_2<3, 0b000110,
                  (ops MEMri:$addr, IntRegs:$src),
                  "sth $src, [$addr]",
-                 [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>;
+                 [(truncstorei16 IntRegs:$src, ADDRri:$addr)]>;
 def STrr  : F3_1<3, 0b000100,
                  (ops MEMrr:$addr, IntRegs:$src),
                  "st $src, [$addr]",
@@ -760,19 +760,19 @@ def : Pat<(call texternalsym:$dst),
 def : Pat<(ret), (RETL)>;
 
 // Map integer extload's to zextloads.
-def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
-def : Pat<(i32 (extload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
-def : Pat<(i32 (extload ADDRrr:$src, i8)), (LDUBrr ADDRrr:$src)>;
-def : Pat<(i32 (extload ADDRri:$src, i8)), (LDUBri ADDRri:$src)>;
-def : Pat<(i32 (extload ADDRrr:$src, i16)), (LDUHrr ADDRrr:$src)>;
-def : Pat<(i32 (extload ADDRri:$src, i16)), (LDUHri ADDRri:$src)>;
+def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
+def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
+def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
+def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
+def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
+def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
 
 // zextload bool -> zextload byte
-def : Pat<(i32 (zextload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
-def : Pat<(i32 (zextload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
+def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
+def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
 
 // truncstore bool -> truncstore byte.
-def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1), 
+def : Pat<(truncstorei1 IntRegs:$src, ADDRrr:$addr),
           (STBrr ADDRrr:$addr, IntRegs:$src)>;
-def : Pat<(truncstore IntRegs:$src, ADDRri:$addr, i1), 
+def : Pat<(truncstorei1 IntRegs:$src, ADDRri:$addr), 
           (STBri ADDRri:$addr, IntRegs:$src)>;