-//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
+//===- SparcInstrInfo.td - Target Description for Sparc Target ------------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// This file describes the SparcV8 instructions in TableGen format.
+// This file describes the Sparc instructions in TableGen format.
//
//===----------------------------------------------------------------------===//
// Instruction format superclass
//===----------------------------------------------------------------------===//
-include "SparcV8InstrFormats.td"
+include "SparcInstrFormats.td"
//===----------------------------------------------------------------------===//
// Feature predicates.
}], HI22>;
// Addressing modes.
-def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>;
-def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>;
+def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", [], []>;
+def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex], []>;
// Address operands
def MEMrr : Operand<i32> {
def brtarget : Operand<OtherVT>;
def calltarget : Operand<i32>;
-def SDTV8cmpfcc :
-SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
-def SDTV8brcc :
-SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
- SDTCisVT<2, FlagVT>]>;
-def SDTV8selectcc :
-SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
- SDTCisVT<3, i32>, SDTCisVT<4, FlagVT>]>;
-def SDTV8FTOI :
+// Operand for printing out a condition code.
+let PrintMethod = "printCCOperand" in
+ def CCOp : Operand<i32>;
+
+def SDTSPcmpfcc :
+SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
+def SDTSPbrcc :
+SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
+def SDTSPselectcc :
+SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
+def SDTSPFTOI :
SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
-def SDTV8ITOF :
+def SDTSPITOF :
SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
-def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>;
-def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc, [SDNPOutFlag]>;
-def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>;
-def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
+def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>;
+def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutFlag]>;
+def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>;
+def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>;
-def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>;
-def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>;
+def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
+def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
-def V8ftoi : SDNode<"V8ISD::FTOI", SDTV8FTOI>;
-def V8itof : SDNode<"V8ISD::ITOF", SDTV8ITOF>;
+def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
+def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
-def V8selecticc : SDNode<"V8ISD::SELECT_ICC", SDTV8selectcc>;
-def V8selectfcc : SDNode<"V8ISD::SELECT_FCC", SDTV8selectcc>;
+def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInFlag]>;
+def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInFlag]>;
// These are target-independent nodes, but have target-specific formats.
-def SDT_V8CallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
-def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>;
-def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>;
-
-def SDT_V8Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
-def call : SDNode<"V8ISD::CALL", SDT_V8Call,
+def SDT_SPCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
+def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeq,
+ [SDNPHasChain, SDNPOutFlag]>;
+def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeq,
+ [SDNPHasChain, SDNPOutFlag]>;
+
+def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
+def call : SDNode<"SPISD::CALL", SDT_SPCall,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
-def SDT_V8RetFlag : SDTypeProfile<0, 0, []>;
-def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag,
+def SDT_SPRetFlag : SDTypeProfile<0, 0, []>;
+def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRetFlag,
[SDNPHasChain, SDNPOptInFlag]>;
//===----------------------------------------------------------------------===//
// SPARC Flag Conditions
//===----------------------------------------------------------------------===//
-// Note that these values must be kept in sync with the V8CC::CondCode enum
+// Note that these values must be kept in sync with the CCOp::CondCode enum
// values.
-class ICC_VAL<int N> : PatLeaf<(i32 N)> {
- int ICCVal = N;
-}
+class ICC_VAL<int N> : PatLeaf<(i32 N)>;
def ICC_NE : ICC_VAL< 9>; // Not Equal
def ICC_E : ICC_VAL< 1>; // Equal
def ICC_G : ICC_VAL<10>; // Greater
def ICC_VC : ICC_VAL<15>; // Overflow Clear
def ICC_VS : ICC_VAL< 7>; // Overflow Set
-class FCC_VAL<int N> : PatLeaf<(i32 N)> {
- int FCCVal = N;
-}
+class FCC_VAL<int N> : PatLeaf<(i32 N)>;
def FCC_U : FCC_VAL<23>; // Unordered
def FCC_G : FCC_VAL<22>; // Greater
def FCC_UG : FCC_VAL<21>; // Unordered or Greater
def FCC_ULE : FCC_VAL<28>; // Unordered or Less or Equal
def FCC_O : FCC_VAL<29>; // Ordered
+//===----------------------------------------------------------------------===//
+// Instruction Class Templates
+//===----------------------------------------------------------------------===//
+
+/// F3_12 multiclass - Define a normal F3_1/F3_2 pattern in one shot.
+multiclass F3_12<string OpcStr, bits<6> Op3Val, SDNode OpNode> {
+ def rr : F3_1<2, Op3Val,
+ (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
+ !strconcat(OpcStr, " $b, $c, $dst"),
+ [(set IntRegs:$dst, (OpNode IntRegs:$b, IntRegs:$c))]>;
+ def ri : F3_2<2, Op3Val,
+ (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+ !strconcat(OpcStr, " $b, $c, $dst"),
+ [(set IntRegs:$dst, (OpNode IntRegs:$b, simm13:$c))]>;
+}
+
+/// F3_12np multiclass - Define a normal F3_1/F3_2 pattern in one shot, with no
+/// pattern.
+multiclass F3_12np<string OpcStr, bits<6> Op3Val> {
+ def rr : F3_1<2, Op3Val,
+ (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
+ !strconcat(OpcStr, " $b, $c, $dst"), []>;
+ def ri : F3_2<2, Op3Val,
+ (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+ !strconcat(OpcStr, " $b, $c, $dst"), []>;
+}
//===----------------------------------------------------------------------===//
// Instructions
// Pseudo instructions.
class Pseudo<dag ops, string asmstr, list<dag> pattern>
- : InstV8<ops, asmstr, pattern>;
+ : InstSP<ops, asmstr, pattern>;
def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt),
"!ADJCALLSTACKDOWN $amt",
- [(callseq_start imm:$amt)]>;
+ [(callseq_start imm:$amt)]>, Imp<[O6],[O6]>;
def ADJCALLSTACKUP : Pseudo<(ops i32imm:$amt),
"!ADJCALLSTACKUP $amt",
- [(callseq_end imm:$amt)]>;
+ [(callseq_end imm:$amt)]>, Imp<[O6],[O6]>;
def IMPLICIT_DEF_Int : Pseudo<(ops IntRegs:$dst),
"!IMPLICIT_DEF $dst",
[(set IntRegs:$dst, (undef))]>;
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
// scheduler into a branch sequence. This has to handle all permutations of
// selection between i32/f32/f64 on ICC and FCC.
-let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
+let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
def SELECT_CC_Int_ICC
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
"; SELECT_CC_Int_ICC PSEUDO!",
- [(set IntRegs:$dst, (V8selecticc IntRegs:$T, IntRegs:$F,
- imm:$Cond, ICC))]>;
+ [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F,
+ imm:$Cond))]>;
def SELECT_CC_Int_FCC
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
"; SELECT_CC_Int_FCC PSEUDO!",
- [(set IntRegs:$dst, (V8selectfcc IntRegs:$T, IntRegs:$F,
- imm:$Cond, FCC))]>;
+ [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F,
+ imm:$Cond))]>;
def SELECT_CC_FP_ICC
: Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
"; SELECT_CC_FP_ICC PSEUDO!",
- [(set FPRegs:$dst, (V8selecticc FPRegs:$T, FPRegs:$F,
- imm:$Cond, ICC))]>;
+ [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F,
+ imm:$Cond))]>;
def SELECT_CC_FP_FCC
: Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
"; SELECT_CC_FP_FCC PSEUDO!",
- [(set FPRegs:$dst, (V8selectfcc FPRegs:$T, FPRegs:$F,
- imm:$Cond, FCC))]>;
+ [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F,
+ imm:$Cond))]>;
def SELECT_CC_DFP_ICC
: Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
"; SELECT_CC_DFP_ICC PSEUDO!",
- [(set DFPRegs:$dst, (V8selecticc DFPRegs:$T, DFPRegs:$F,
- imm:$Cond, ICC))]>;
+ [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F,
+ imm:$Cond))]>;
def SELECT_CC_DFP_FCC
: Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
"; SELECT_CC_DFP_FCC PSEUDO!",
- [(set DFPRegs:$dst, (V8selectfcc DFPRegs:$T, DFPRegs:$F,
- imm:$Cond, FCC))]>;
+ [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F,
+ imm:$Cond))]>;
}
def LDSBrr : F3_1<3, 0b001001,
(ops IntRegs:$dst, MEMrr:$addr),
"ldsb [$addr], $dst",
- [(set IntRegs:$dst, (sextload ADDRrr:$addr, i8))]>;
+ [(set IntRegs:$dst, (sextloadi8 ADDRrr:$addr))]>;
def LDSBri : F3_2<3, 0b001001,
(ops IntRegs:$dst, MEMri:$addr),
"ldsb [$addr], $dst",
- [(set IntRegs:$dst, (sextload ADDRri:$addr, i8))]>;
+ [(set IntRegs:$dst, (sextloadi8 ADDRri:$addr))]>;
def LDSHrr : F3_1<3, 0b001010,
(ops IntRegs:$dst, MEMrr:$addr),
"ldsh [$addr], $dst",
- [(set IntRegs:$dst, (sextload ADDRrr:$addr, i16))]>;
+ [(set IntRegs:$dst, (sextloadi16 ADDRrr:$addr))]>;
def LDSHri : F3_2<3, 0b001010,
(ops IntRegs:$dst, MEMri:$addr),
"ldsh [$addr], $dst",
- [(set IntRegs:$dst, (sextload ADDRri:$addr, i16))]>;
+ [(set IntRegs:$dst, (sextloadi16 ADDRri:$addr))]>;
def LDUBrr : F3_1<3, 0b000001,
(ops IntRegs:$dst, MEMrr:$addr),
"ldub [$addr], $dst",
- [(set IntRegs:$dst, (zextload ADDRrr:$addr, i8))]>;
+ [(set IntRegs:$dst, (zextloadi8 ADDRrr:$addr))]>;
def LDUBri : F3_2<3, 0b000001,
(ops IntRegs:$dst, MEMri:$addr),
"ldub [$addr], $dst",
- [(set IntRegs:$dst, (zextload ADDRri:$addr, i8))]>;
+ [(set IntRegs:$dst, (zextloadi8 ADDRri:$addr))]>;
def LDUHrr : F3_1<3, 0b000010,
(ops IntRegs:$dst, MEMrr:$addr),
"lduh [$addr], $dst",
- [(set IntRegs:$dst, (zextload ADDRrr:$addr, i16))]>;
+ [(set IntRegs:$dst, (zextloadi16 ADDRrr:$addr))]>;
def LDUHri : F3_2<3, 0b000010,
(ops IntRegs:$dst, MEMri:$addr),
"lduh [$addr], $dst",
- [(set IntRegs:$dst, (zextload ADDRri:$addr, i16))]>;
+ [(set IntRegs:$dst, (zextloadi16 ADDRri:$addr))]>;
def LDrr : F3_1<3, 0b000000,
(ops IntRegs:$dst, MEMrr:$addr),
"ld [$addr], $dst",
def STBrr : F3_1<3, 0b000101,
(ops MEMrr:$addr, IntRegs:$src),
"stb $src, [$addr]",
- [(truncstore IntRegs:$src, ADDRrr:$addr, i8)]>;
+ [(truncstorei8 IntRegs:$src, ADDRrr:$addr)]>;
def STBri : F3_2<3, 0b000101,
(ops MEMri:$addr, IntRegs:$src),
"stb $src, [$addr]",
- [(truncstore IntRegs:$src, ADDRri:$addr, i8)]>;
+ [(truncstorei8 IntRegs:$src, ADDRri:$addr)]>;
def STHrr : F3_1<3, 0b000110,
(ops MEMrr:$addr, IntRegs:$src),
"sth $src, [$addr]",
- [(truncstore IntRegs:$src, ADDRrr:$addr, i16)]>;
+ [(truncstorei16 IntRegs:$src, ADDRrr:$addr)]>;
def STHri : F3_2<3, 0b000110,
(ops MEMri:$addr, IntRegs:$src),
"sth $src, [$addr]",
- [(truncstore IntRegs:$src, ADDRri:$addr, i16)]>;
+ [(truncstorei16 IntRegs:$src, ADDRri:$addr)]>;
def STrr : F3_1<3, 0b000100,
(ops MEMrr:$addr, IntRegs:$src),
"st $src, [$addr]",
def NOP : F2_1<0b100, (ops), "nop", []>;
// Section B.11 - Logical Instructions, p. 106
-def ANDrr : F3_1<2, 0b000001,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "and $b, $c, $dst",
- [(set IntRegs:$dst, (and IntRegs:$b, IntRegs:$c))]>;
-def ANDri : F3_2<2, 0b000001,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "and $b, $c, $dst",
- [(set IntRegs:$dst, (and IntRegs:$b, simm13:$c))]>;
+defm AND : F3_12<"and", 0b000001, and>;
+
def ANDNrr : F3_1<2, 0b000101,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
"andn $b, $c, $dst",
def ANDNri : F3_2<2, 0b000101,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
"andn $b, $c, $dst", []>;
-def ORrr : F3_1<2, 0b000010,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "or $b, $c, $dst",
- [(set IntRegs:$dst, (or IntRegs:$b, IntRegs:$c))]>;
-def ORri : F3_2<2, 0b000010,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "or $b, $c, $dst",
- [(set IntRegs:$dst, (or IntRegs:$b, simm13:$c))]>;
+
+defm OR : F3_12<"or", 0b000010, or>;
+
def ORNrr : F3_1<2, 0b000110,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
"orn $b, $c, $dst",
def ORNri : F3_2<2, 0b000110,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
"orn $b, $c, $dst", []>;
-def XORrr : F3_1<2, 0b000011,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "xor $b, $c, $dst",
- [(set IntRegs:$dst, (xor IntRegs:$b, IntRegs:$c))]>;
-def XORri : F3_2<2, 0b000011,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "xor $b, $c, $dst",
- [(set IntRegs:$dst, (xor IntRegs:$b, simm13:$c))]>;
+defm XOR : F3_12<"xor", 0b000011, xor>;
+
def XNORrr : F3_1<2, 0b000111,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
"xnor $b, $c, $dst",
"xnor $b, $c, $dst", []>;
// Section B.12 - Shift Instructions, p. 107
-def SLLrr : F3_1<2, 0b100101,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "sll $b, $c, $dst",
- [(set IntRegs:$dst, (shl IntRegs:$b, IntRegs:$c))]>;
-def SLLri : F3_2<2, 0b100101,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "sll $b, $c, $dst",
- [(set IntRegs:$dst, (shl IntRegs:$b, simm13:$c))]>;
-def SRLrr : F3_1<2, 0b100110,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "srl $b, $c, $dst",
- [(set IntRegs:$dst, (srl IntRegs:$b, IntRegs:$c))]>;
-def SRLri : F3_2<2, 0b100110,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "srl $b, $c, $dst",
- [(set IntRegs:$dst, (srl IntRegs:$b, simm13:$c))]>;
-def SRArr : F3_1<2, 0b100111,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "sra $b, $c, $dst",
- [(set IntRegs:$dst, (sra IntRegs:$b, IntRegs:$c))]>;
-def SRAri : F3_2<2, 0b100111,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "sra $b, $c, $dst",
- [(set IntRegs:$dst, (sra IntRegs:$b, simm13:$c))]>;
+defm SLL : F3_12<"sll", 0b100101, shl>;
+defm SRL : F3_12<"srl", 0b100110, srl>;
+defm SRA : F3_12<"sra", 0b100111, sra>;
// Section B.13 - Add Instructions, p. 108
-def ADDrr : F3_1<2, 0b000000,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "add $b, $c, $dst",
- [(set IntRegs:$dst, (add IntRegs:$b, IntRegs:$c))]>;
-def ADDri : F3_2<2, 0b000000,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "add $b, $c, $dst",
- [(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>;
-def ADDCCrr : F3_1<2, 0b010000,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "addcc $b, $c, $dst", []>;
-def ADDCCri : F3_2<2, 0b010000,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "addcc $b, $c, $dst", []>;
-def ADDXrr : F3_1<2, 0b001000,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "addx $b, $c, $dst", []>;
-def ADDXri : F3_2<2, 0b001000,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "addx $b, $c, $dst", []>;
+defm ADD : F3_12<"add", 0b000000, add>;
+
+// "LEA" forms of add (patterns to make tblgen happy)
+def LEA_ADDri : F3_2<2, 0b000000,
+ (ops IntRegs:$dst, MEMri:$addr),
+ "add ${addr:arith}, $dst",
+ [(set IntRegs:$dst, ADDRri:$addr)]>;
+
+defm ADDCC : F3_12<"addcc", 0b010000, addc>;
+defm ADDX : F3_12<"addx", 0b001000, adde>;
// Section B.15 - Subtract Instructions, p. 110
-def SUBrr : F3_1<2, 0b000100,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "sub $b, $c, $dst",
- [(set IntRegs:$dst, (sub IntRegs:$b, IntRegs:$c))]>;
-def SUBri : F3_2<2, 0b000100,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "sub $b, $c, $dst",
- [(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
-def SUBXrr : F3_1<2, 0b001100,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "subx $b, $c, $dst", []>;
-def SUBXri : F3_2<2, 0b001100,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "subx $b, $c, $dst", []>;
-def SUBCCrr : F3_1<2, 0b010100,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "subcc $b, $c, $dst",
- [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, IntRegs:$c))]>;
-def SUBCCri : F3_2<2, 0b010100,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "subcc $b, $c, $dst",
- [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, simm13:$c))]>;
+defm SUB : F3_12 <"sub" , 0b000100, sub>;
+defm SUBX : F3_12 <"subx" , 0b001100, sube>;
+defm SUBCC : F3_12 <"subcc", 0b010100, SPcmpicc>;
+
def SUBXCCrr: F3_1<2, 0b011100,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
"subxcc $b, $c, $dst", []>;
// Section B.18 - Multiply Instructions, p. 113
-def UMULrr : F3_1<2, 0b001010,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "umul $b, $c, $dst", []>;
-def UMULri : F3_2<2, 0b001010,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "umul $b, $c, $dst", []>;
-def SMULrr : F3_1<2, 0b001011,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "smul $b, $c, $dst",
- [(set IntRegs:$dst, (mul IntRegs:$b, IntRegs:$c))]>;
-def SMULri : F3_2<2, 0b001011,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "smul $b, $c, $dst",
- [(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>;
+defm UMUL : F3_12np<"umul", 0b001010>;
+defm SMUL : F3_12 <"smul", 0b001011, mul>;
+
// Section B.19 - Divide Instructions, p. 115
-def UDIVrr : F3_1<2, 0b001110,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "udiv $b, $c, $dst", []>;
-def UDIVri : F3_2<2, 0b001110,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "udiv $b, $c, $dst", []>;
-def SDIVrr : F3_1<2, 0b001111,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "sdiv $b, $c, $dst", []>;
-def SDIVri : F3_2<2, 0b001111,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "sdiv $b, $c, $dst", []>;
+defm UDIV : F3_12np<"udiv", 0b001110>;
+defm SDIV : F3_12np<"sdiv", 0b001111>;
// Section B.20 - SAVE and RESTORE, p. 117
-def SAVErr : F3_1<2, 0b111100,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "save $b, $c, $dst", []>;
-def SAVEri : F3_2<2, 0b111100,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "save $b, $c, $dst", []>;
-def RESTORErr : F3_1<2, 0b111101,
- (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "restore $b, $c, $dst", []>;
-def RESTOREri : F3_2<2, 0b111101,
- (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "restore $b, $c, $dst", []>;
+defm SAVE : F3_12np<"save" , 0b111100>;
+defm RESTORE : F3_12np<"restore", 0b111101>;
// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
// conditional branch class:
-class BranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
+class BranchSP<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
: F2_2<cc, 0b010, ops, asmstr, pattern> {
let isBranch = 1;
let isTerminator = 1;
}
let isBarrier = 1 in
- def BA : BranchV8<0b1000, (ops brtarget:$dst),
+ def BA : BranchSP<0b1000, (ops brtarget:$dst),
"ba $dst",
[(br bb:$dst)]>;
-def BNE : BranchV8<0b1001, (ops brtarget:$dst),
- "bne $dst",
- [(V8bricc bb:$dst, ICC_NE, ICC)]>;
-def BE : BranchV8<0b0001, (ops brtarget:$dst),
- "be $dst",
- [(V8bricc bb:$dst, ICC_E, ICC)]>;
-def BG : BranchV8<0b1010, (ops brtarget:$dst),
- "bg $dst",
- [(V8bricc bb:$dst, ICC_G, ICC)]>;
-def BLE : BranchV8<0b0010, (ops brtarget:$dst),
- "ble $dst",
- [(V8bricc bb:$dst, ICC_LE, ICC)]>;
-def BGE : BranchV8<0b1011, (ops brtarget:$dst),
- "bge $dst",
- [(V8bricc bb:$dst, ICC_GE, ICC)]>;
-def BL : BranchV8<0b0011, (ops brtarget:$dst),
- "bl $dst",
- [(V8bricc bb:$dst, ICC_L, ICC)]>;
-def BGU : BranchV8<0b1100, (ops brtarget:$dst),
- "bgu $dst",
- [(V8bricc bb:$dst, ICC_GU, ICC)]>;
-def BLEU : BranchV8<0b0100, (ops brtarget:$dst),
- "bleu $dst",
- [(V8bricc bb:$dst, ICC_LEU, ICC)]>;
-def BCC : BranchV8<0b1101, (ops brtarget:$dst),
- "bcc $dst",
- [(V8bricc bb:$dst, ICC_CC, ICC)]>;
-def BCS : BranchV8<0b0101, (ops brtarget:$dst),
- "bcs $dst",
- [(V8bricc bb:$dst, ICC_CS, ICC)]>;
-def BPOS : BranchV8<0b1110, (ops brtarget:$dst),
- "bpos $dst",
- [(V8bricc bb:$dst, ICC_POS, ICC)]>;
-def BNEG : BranchV8<0b0110, (ops brtarget:$dst),
- "bneg $dst",
- [(V8bricc bb:$dst, ICC_NEG, ICC)]>;
-def BVC : BranchV8<0b1111, (ops brtarget:$dst),
- "bvc $dst",
- [(V8bricc bb:$dst, ICC_VC, ICC)]>;
-def BVS : BranchV8<0b0111, (ops brtarget:$dst),
- "bvs $dst",
- [(V8bricc bb:$dst, ICC_VS, ICC)]>;
-
+
+// FIXME: the encoding for the JIT should look at the condition field.
+def BCOND : BranchSP<0, (ops brtarget:$dst, CCOp:$cc),
+ "b$cc $dst",
+ [(SPbricc bb:$dst, imm:$cc)]>;
// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
// floating-point conditional branch class:
-class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
+class FPBranchSP<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
: F2_2<cc, 0b110, ops, asmstr, pattern> {
let isBranch = 1;
let isTerminator = 1;
let noResults = 1;
}
-def FBU : FPBranchV8<0b0111, (ops brtarget:$dst),
- "fbu $dst",
- [(V8brfcc bb:$dst, FCC_U, FCC)]>;
-def FBG : FPBranchV8<0b0110, (ops brtarget:$dst),
- "fbg $dst",
- [(V8brfcc bb:$dst, FCC_G, FCC)]>;
-def FBUG : FPBranchV8<0b0101, (ops brtarget:$dst),
- "fbug $dst",
- [(V8brfcc bb:$dst, FCC_UG, FCC)]>;
-def FBL : FPBranchV8<0b0100, (ops brtarget:$dst),
- "fbl $dst",
- [(V8brfcc bb:$dst, FCC_L, FCC)]>;
-def FBUL : FPBranchV8<0b0011, (ops brtarget:$dst),
- "fbul $dst",
- [(V8brfcc bb:$dst, FCC_UL, FCC)]>;
-def FBLG : FPBranchV8<0b0010, (ops brtarget:$dst),
- "fblg $dst",
- [(V8brfcc bb:$dst, FCC_LG, FCC)]>;
-def FBNE : FPBranchV8<0b0001, (ops brtarget:$dst),
- "fbne $dst",
- [(V8brfcc bb:$dst, FCC_NE, FCC)]>;
-def FBE : FPBranchV8<0b1001, (ops brtarget:$dst),
- "fbe $dst",
- [(V8brfcc bb:$dst, FCC_E, FCC)]>;
-def FBUE : FPBranchV8<0b1010, (ops brtarget:$dst),
- "fbue $dst",
- [(V8brfcc bb:$dst, FCC_UE, FCC)]>;
-def FBGE : FPBranchV8<0b1011, (ops brtarget:$dst),
- "fbge $dst",
- [(V8brfcc bb:$dst, FCC_GE, FCC)]>;
-def FBUGE: FPBranchV8<0b1100, (ops brtarget:$dst),
- "fbuge $dst",
- [(V8brfcc bb:$dst, FCC_UGE, FCC)]>;
-def FBLE : FPBranchV8<0b1101, (ops brtarget:$dst),
- "fble $dst",
- [(V8brfcc bb:$dst, FCC_LE, FCC)]>;
-def FBULE: FPBranchV8<0b1110, (ops brtarget:$dst),
- "fbule $dst",
- [(V8brfcc bb:$dst, FCC_ULE, FCC)]>;
-def FBO : FPBranchV8<0b1111, (ops brtarget:$dst),
- "fbo $dst",
- [(V8brfcc bb:$dst, FCC_O, FCC)]>;
-
+// FIXME: the encoding for the JIT should look at the condition field.
+def FBCOND : FPBranchSP<0, (ops brtarget:$dst, CCOp:$cc),
+ "fb$cc $dst",
+ [(SPbrfcc bb:$dst, imm:$cc)]>;
// Section B.24 - Call and Link Instruction, p. 125
hasDelaySlot = 1, isCall = 1, noResults = 1,
Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
- def CALL : InstV8<(ops calltarget:$dst),
+ def CALL : InstSP<(ops calltarget:$dst),
"call $dst", []> {
bits<30> disp;
let op = 1;
def FITOS : F3_3<2, 0b110100, 0b011000100,
(ops FPRegs:$dst, FPRegs:$src),
"fitos $src, $dst",
- [(set FPRegs:$dst, (V8itof FPRegs:$src))]>;
+ [(set FPRegs:$dst, (SPitof FPRegs:$src))]>;
def FITOD : F3_3<2, 0b110100, 0b011001000,
(ops DFPRegs:$dst, FPRegs:$src),
"fitod $src, $dst",
- [(set DFPRegs:$dst, (V8itof FPRegs:$src))]>;
+ [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>;
// Convert Floating-point to Integer Instructions, p. 142
def FSTOI : F3_3<2, 0b110100, 0b011010001,
(ops FPRegs:$dst, FPRegs:$src),
"fstoi $src, $dst",
- [(set FPRegs:$dst, (V8ftoi FPRegs:$src))]>;
+ [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>;
def FDTOI : F3_3<2, 0b110100, 0b011010010,
(ops FPRegs:$dst, DFPRegs:$src),
"fdtoi $src, $dst",
- [(set FPRegs:$dst, (V8ftoi DFPRegs:$src))]>;
+ [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>;
// Convert between Floating-point Formats Instructions, p. 143
def FSTOD : F3_3<2, 0b110100, 0b011001001,
def FCMPS : F3_3<2, 0b110101, 0b001010001,
(ops FPRegs:$src1, FPRegs:$src2),
"fcmps $src1, $src2\n\tnop",
- [(set FCC, (V8cmpfcc FPRegs:$src1, FPRegs:$src2))]>;
+ [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>;
def FCMPD : F3_3<2, 0b110101, 0b001010010,
(ops DFPRegs:$src1, DFPRegs:$src2),
"fcmpd $src1, $src2\n\tnop",
- [(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>;
+ [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>;
//===----------------------------------------------------------------------===//
let Predicates = [HasV9], isTwoAddress = 1 in {
// Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
// FIXME: Add instruction encodings for the JIT some day.
- class IntCMOVICCrr<string asmstr, ICC_VAL CC>
- : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), asmstr,
+ def MOVICCrr
+ : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, CCOp:$cc),
+ "mov$cc %icc, $F, $dst",
[(set IntRegs:$dst,
- (V8selecticc IntRegs:$F, IntRegs:$T, CC, ICC))]> {
- int CondBits = CC.ICCVal;
- }
- class IntCMOVICCri<string asmstr, ICC_VAL CC>
- : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F), asmstr,
+ (SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
+ def MOVICCri
+ : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, CCOp:$cc),
+ "mov$cc %icc, $F, $dst",
[(set IntRegs:$dst,
- (V8selecticc simm11:$F, IntRegs:$T, CC, ICC))]> {
- int CondBits = CC.ICCVal;
- }
-
- // MOV*rr instructions.
- def MOVNErr : IntCMOVICCrr< "movne %icc, $F, $dst", ICC_NE>;
- def MOVErr : IntCMOVICCrr< "move %icc, $F, $dst", ICC_E>;
- def MOVGrr : IntCMOVICCrr< "movg %icc, $F, $dst", ICC_G>;
- def MOVLErr : IntCMOVICCrr< "movle %icc, $F, $dst", ICC_LE>;
- def MOVGErr : IntCMOVICCrr< "movge %icc, $F, $dst", ICC_GE>;
- def MOVLrr : IntCMOVICCrr< "movl %icc, $F, $dst", ICC_L>;
- def MOVGUrr : IntCMOVICCrr< "movgu %icc, $F, $dst", ICC_GU>;
- def MOVLEUrr : IntCMOVICCrr<"movleu %icc, $F, $dst", ICC_LEU>;
- def MOVCCrr : IntCMOVICCrr< "movcc %icc, $F, $dst", ICC_CC>;
- def MOVCSrr : IntCMOVICCrr< "movcs %icc, $F, $dst", ICC_CS>;
- def MOVPOSrr : IntCMOVICCrr<"movpos %icc, $F, $dst", ICC_POS>;
- def MOVNEGrr : IntCMOVICCrr<"movneg %icc, $F, $dst", ICC_NEG>;
- def MOVVCrr : IntCMOVICCrr< "movvc %icc, $F, $dst", ICC_VC>;
- def MOVVSrr : IntCMOVICCrr< "movvs %icc, $F, $dst", ICC_VS>;
-
- // MOV*ri instructions.
- def MOVNEri : IntCMOVICCri< "movne %icc, $F, $dst", ICC_NE>;
- def MOVEri : IntCMOVICCri< "move %icc, $F, $dst", ICC_E>;
- def MOVGri : IntCMOVICCri< "movg %icc, $F, $dst", ICC_G>;
- def MOVLEri : IntCMOVICCri< "movle %icc, $F, $dst", ICC_LE>;
- def MOVGEri : IntCMOVICCri< "movge %icc, $F, $dst", ICC_GE>;
- def MOVLri : IntCMOVICCri< "movl %icc, $F, $dst", ICC_L>;
- def MOVGUri : IntCMOVICCri< "movgu %icc, $F, $dst", ICC_GU>;
- def MOVLEUri : IntCMOVICCri<"movleu %icc, $F, $dst", ICC_LEU>;
- def MOVCCri : IntCMOVICCri< "movcc %icc, $F, $dst", ICC_CC>;
- def MOVCSri : IntCMOVICCri< "movcs %icc, $F, $dst", ICC_CS>;
- def MOVPOSri : IntCMOVICCri<"movpos %icc, $F, $dst", ICC_POS>;
- def MOVNEGri : IntCMOVICCri<"movneg %icc, $F, $dst", ICC_NEG>;
- def MOVVCri : IntCMOVICCri< "movvc %icc, $F, $dst", ICC_VC>;
- def MOVVSri : IntCMOVICCri< "movvs %icc, $F, $dst", ICC_VS>;
-
- // FIXME: Allow regalloc of the fcc condition code some day.
- class IntCMOVFCCrr<string asmstr, FCC_VAL CC>
- : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F), asmstr,
+ (SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>;
+
+ def MOVFCCrr
+ : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, CCOp:$cc),
+ "mov$cc %fcc0, $F, $dst",
[(set IntRegs:$dst,
- (V8selectfcc IntRegs:$F, IntRegs:$T, CC, FCC))]> {
- int CondBits = CC.FCCVal;
- }
- class IntCMOVFCCri<string asmstr, FCC_VAL CC>
- : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F), asmstr,
+ (SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
+ def MOVFCCri
+ : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, CCOp:$cc),
+ "mov$cc %fcc0, $F, $dst",
[(set IntRegs:$dst,
- (V8selectfcc simm11:$F, IntRegs:$T, CC, FCC))]> {
- int CondBits = CC.FCCVal;
- }
+ (SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>;
+
+ def FMOVS_ICC
+ : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, CCOp:$cc),
+ "fmovs$cc %icc, $F, $dst",
+ [(set FPRegs:$dst,
+ (SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
+ def FMOVD_ICC
+ : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
+ "fmovd$cc %icc, $F, $dst",
+ [(set DFPRegs:$dst,
+ (SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
+ def FMOVS_FCC
+ : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, CCOp:$cc),
+ "fmovs$cc %fcc0, $F, $dst",
+ [(set FPRegs:$dst,
+ (SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
+ def FMOVD_FCC
+ : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
+ "fmovd$cc %fcc0, $F, $dst",
+ [(set DFPRegs:$dst,
+ (SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
- // MOVF*rr instructions.
- def MOVFUrr : IntCMOVFCCrr< "movfu %fcc, $F, $dst", FCC_U>;
- def MOVFGrr : IntCMOVFCCrr< "movfg %fcc, $F, $dst", FCC_G>;
- def MOVFUGrr : IntCMOVFCCrr< "movfug %fcc, $F, $dst", FCC_UG>;
- def MOVFLrr : IntCMOVFCCrr< "movfl %fcc, $F, $dst", FCC_L>;
- def MOVFULrr : IntCMOVFCCrr< "movful %fcc, $F, $dst", FCC_UL>;
- def MOVFLGrr : IntCMOVFCCrr< "movflg %fcc, $F, $dst", FCC_LG>;
- def MOVFNErr : IntCMOVFCCrr< "movfne %fcc, $F, $dst", FCC_NE>;
- def MOVFErr : IntCMOVFCCrr< "movfe %fcc, $F, $dst", FCC_E>;
- def MOVFUErr : IntCMOVFCCrr< "movfue %fcc, $F, $dst", FCC_UE>;
- def MOVFGErr : IntCMOVFCCrr< "movfge %fcc, $F, $dst", FCC_GE>;
- def MOVFUGErr : IntCMOVFCCrr<"movfuge %fcc, $F, $dst", FCC_UGE>;
- def MOVFLErr : IntCMOVFCCrr< "movfle %fcc, $F, $dst", FCC_LE>;
- def MOVFULErr : IntCMOVFCCrr<"movfule %fcc, $F, $dst", FCC_ULE>;
- def MOVFOrr : IntCMOVFCCrr< "movfo %fcc, $F, $dst", FCC_O>;
-
- // MOVF*ri instructions.
- def MOVFUri : IntCMOVFCCri< "movfu %fcc, $F, $dst", FCC_U>;
- def MOVFGri : IntCMOVFCCri< "movfg %fcc, $F, $dst", FCC_G>;
- def MOVFUGri : IntCMOVFCCri< "movfug %fcc, $F, $dst", FCC_UG>;
- def MOVFLri : IntCMOVFCCri< "movfl %fcc, $F, $dst", FCC_L>;
- def MOVFULri : IntCMOVFCCri< "movful %fcc, $F, $dst", FCC_UL>;
- def MOVFLGri : IntCMOVFCCri< "movflg %fcc, $F, $dst", FCC_LG>;
- def MOVFNEri : IntCMOVFCCri< "movfne %fcc, $F, $dst", FCC_NE>;
- def MOVFEri : IntCMOVFCCri< "movfe %fcc, $F, $dst", FCC_E>;
- def MOVFUEri : IntCMOVFCCri< "movfue %fcc, $F, $dst", FCC_UE>;
- def MOVFGEri : IntCMOVFCCri< "movfge %fcc, $F, $dst", FCC_GE>;
- def MOVFUGEri : IntCMOVFCCri<"movfuge %fcc, $F, $dst", FCC_UGE>;
- def MOVFLEri : IntCMOVFCCri< "movfle %fcc, $F, $dst", FCC_LE>;
- def MOVFULEri : IntCMOVFCCri<"movfule %fcc, $F, $dst", FCC_ULE>;
- def MOVFOri : IntCMOVFCCri< "movfo %fcc, $F, $dst", FCC_O>;
}
// Floating-Point Move Instructions, p. 164 of the V9 manual.
def : Pat<(i32 imm:$val),
(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
+// subc
+def : Pat<(subc IntRegs:$b, IntRegs:$c),
+ (SUBCCrr IntRegs:$b, IntRegs:$c)>;
+def : Pat<(subc IntRegs:$b, simm13:$val),
+ (SUBCCri IntRegs:$b, imm:$val)>;
+
// Global addresses, constant pool entries
-def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
-def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
-def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>;
-def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;
+def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
+def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
+def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
+def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>;
// Add reg, lo. This is used when taking the addr of a global/constpool entry.
-def : Pat<(add IntRegs:$r, (V8lo tglobaladdr:$in)),
+def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)),
(ADDri IntRegs:$r, tglobaladdr:$in)>;
-def : Pat<(add IntRegs:$r, (V8lo tconstpool:$in)),
+def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)),
(ADDri IntRegs:$r, tconstpool:$in)>;
-
// Calls:
def : Pat<(call tglobaladdr:$dst),
(CALL tglobaladdr:$dst)>;
-def : Pat<(call externalsym:$dst),
- (CALL externalsym:$dst)>;
+def : Pat<(call texternalsym:$dst),
+ (CALL texternalsym:$dst)>;
def : Pat<(ret), (RETL)>;
// Map integer extload's to zextloads.
-def : Pat<(i32 (extload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
-def : Pat<(i32 (extload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
-def : Pat<(i32 (extload ADDRrr:$src, i8)), (LDUBrr ADDRrr:$src)>;
-def : Pat<(i32 (extload ADDRri:$src, i8)), (LDUBri ADDRri:$src)>;
-def : Pat<(i32 (extload ADDRrr:$src, i16)), (LDUHrr ADDRrr:$src)>;
-def : Pat<(i32 (extload ADDRri:$src, i16)), (LDUHri ADDRri:$src)>;
+def : Pat<(i32 (extloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
+def : Pat<(i32 (extloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
+def : Pat<(i32 (extloadi8 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
+def : Pat<(i32 (extloadi8 ADDRri:$src)), (LDUBri ADDRri:$src)>;
+def : Pat<(i32 (extloadi16 ADDRrr:$src)), (LDUHrr ADDRrr:$src)>;
+def : Pat<(i32 (extloadi16 ADDRri:$src)), (LDUHri ADDRri:$src)>;
// zextload bool -> zextload byte
-def : Pat<(i32 (zextload ADDRrr:$src, i1)), (LDUBrr ADDRrr:$src)>;
-def : Pat<(i32 (zextload ADDRri:$src, i1)), (LDUBri ADDRri:$src)>;
+def : Pat<(i32 (zextloadi1 ADDRrr:$src)), (LDUBrr ADDRrr:$src)>;
+def : Pat<(i32 (zextloadi1 ADDRri:$src)), (LDUBri ADDRri:$src)>;
// truncstore bool -> truncstore byte.
-def : Pat<(truncstore IntRegs:$src, ADDRrr:$addr, i1),
+def : Pat<(truncstorei1 IntRegs:$src, ADDRrr:$addr),
(STBrr ADDRrr:$addr, IntRegs:$src)>;
-def : Pat<(truncstore IntRegs:$src, ADDRri:$addr, i1),
+def : Pat<(truncstorei1 IntRegs:$src, ADDRri:$addr),
(STBri ADDRri:$addr, IntRegs:$src)>;