-//===- SparcV8Instrs.td - Target Description for SparcV8 Target -----------===//
+//===- SparcInstrInfo.td - Target Description for Sparc Target ------------===//
//
// The LLVM Compiler Infrastructure
//
//
//===----------------------------------------------------------------------===//
//
-// This file describes the SparcV8 instructions in TableGen format.
+// This file describes the Sparc instructions in TableGen format.
//
//===----------------------------------------------------------------------===//
// Instruction format superclass
//===----------------------------------------------------------------------===//
-include "SparcV8InstrFormats.td"
+include "SparcInstrFormats.td"
//===----------------------------------------------------------------------===//
// Feature predicates.
// Addressing modes.
def ADDRrr : ComplexPattern<i32, 2, "SelectADDRrr", []>;
-def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", []>;
+def ADDRri : ComplexPattern<i32, 2, "SelectADDRri", [frameindex]>;
// Address operands
def MEMrr : Operand<i32> {
def brtarget : Operand<OtherVT>;
def calltarget : Operand<i32>;
-def SDTV8cmpfcc :
-SDTypeProfile<1, 2, [SDTCisVT<0, FlagVT>, SDTCisFP<1>, SDTCisSameAs<1, 2>]>;
-def SDTV8brcc :
-SDTypeProfile<0, 3, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>,
- SDTCisVT<2, FlagVT>]>;
-def SDTV8selectcc :
-SDTypeProfile<1, 4, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>,
- SDTCisVT<3, i32>, SDTCisVT<4, FlagVT>]>;
-def SDTV8FTOI :
+// Operand for printing out a condition code.
+let PrintMethod = "printCCOperand" in
+ def CCOp : Operand<i32>;
+
+def SDTSPcmpfcc :
+SDTypeProfile<0, 2, [SDTCisFP<0>, SDTCisSameAs<0, 1>]>;
+def SDTSPbrcc :
+SDTypeProfile<0, 2, [SDTCisVT<0, OtherVT>, SDTCisVT<1, i32>]>;
+def SDTSPselectcc :
+SDTypeProfile<1, 3, [SDTCisSameAs<0, 1>, SDTCisSameAs<1, 2>, SDTCisVT<3, i32>]>;
+def SDTSPFTOI :
SDTypeProfile<1, 1, [SDTCisVT<0, f32>, SDTCisFP<1>]>;
-def SDTV8ITOF :
+def SDTSPITOF :
SDTypeProfile<1, 1, [SDTCisFP<0>, SDTCisVT<1, f32>]>;
-def V8cmpicc : SDNode<"V8ISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>;
-def V8cmpfcc : SDNode<"V8ISD::CMPFCC", SDTV8cmpfcc, [SDNPOutFlag]>;
-def V8bricc : SDNode<"V8ISD::BRICC", SDTV8brcc, [SDNPHasChain]>;
-def V8brfcc : SDNode<"V8ISD::BRFCC", SDTV8brcc, [SDNPHasChain]>;
+def SPcmpicc : SDNode<"SPISD::CMPICC", SDTIntBinOp, [SDNPOutFlag]>;
+def SPcmpfcc : SDNode<"SPISD::CMPFCC", SDTSPcmpfcc, [SDNPOutFlag]>;
+def SPbricc : SDNode<"SPISD::BRICC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>;
+def SPbrfcc : SDNode<"SPISD::BRFCC", SDTSPbrcc, [SDNPHasChain, SDNPInFlag]>;
-def V8hi : SDNode<"V8ISD::Hi", SDTIntUnaryOp>;
-def V8lo : SDNode<"V8ISD::Lo", SDTIntUnaryOp>;
+def SPhi : SDNode<"SPISD::Hi", SDTIntUnaryOp>;
+def SPlo : SDNode<"SPISD::Lo", SDTIntUnaryOp>;
-def V8ftoi : SDNode<"V8ISD::FTOI", SDTV8FTOI>;
-def V8itof : SDNode<"V8ISD::ITOF", SDTV8ITOF>;
+def SPftoi : SDNode<"SPISD::FTOI", SDTSPFTOI>;
+def SPitof : SDNode<"SPISD::ITOF", SDTSPITOF>;
-def V8selecticc : SDNode<"V8ISD::SELECT_ICC", SDTV8selectcc>;
-def V8selectfcc : SDNode<"V8ISD::SELECT_FCC", SDTV8selectcc>;
+def SPselecticc : SDNode<"SPISD::SELECT_ICC", SDTSPselectcc, [SDNPInFlag]>;
+def SPselectfcc : SDNode<"SPISD::SELECT_FCC", SDTSPselectcc, [SDNPInFlag]>;
// These are target-independent nodes, but have target-specific formats.
-def SDT_V8CallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
-def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_V8CallSeq, [SDNPHasChain]>;
-def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_V8CallSeq, [SDNPHasChain]>;
+def SDT_SPCallSeq : SDTypeProfile<0, 1, [ SDTCisVT<0, i32> ]>;
+def callseq_start : SDNode<"ISD::CALLSEQ_START", SDT_SPCallSeq, [SDNPHasChain]>;
+def callseq_end : SDNode<"ISD::CALLSEQ_END", SDT_SPCallSeq, [SDNPHasChain]>;
-def SDT_V8Call : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
-def call : SDNode<"V8ISD::CALL", SDT_V8Call,
+def SDT_SPCall : SDTypeProfile<0, 1, [SDTCisVT<0, i32>]>;
+def call : SDNode<"SPISD::CALL", SDT_SPCall,
[SDNPHasChain, SDNPOptInFlag, SDNPOutFlag]>;
-def SDT_V8RetFlag : SDTypeProfile<0, 0, []>;
-def retflag : SDNode<"V8ISD::RET_FLAG", SDT_V8RetFlag,
+def SDT_SPRetFlag : SDTypeProfile<0, 0, []>;
+def retflag : SDNode<"SPISD::RET_FLAG", SDT_SPRetFlag,
[SDNPHasChain, SDNPOptInFlag]>;
//===----------------------------------------------------------------------===//
// SPARC Flag Conditions
//===----------------------------------------------------------------------===//
-// Note that these values must be kept in sync with the V8CC::CondCode enum
+// Note that these values must be kept in sync with the CCOp::CondCode enum
// values.
-class ICC_VAL<int N> : PatLeaf<(i32 N)> {
- int ICCVal = N;
-}
+class ICC_VAL<int N> : PatLeaf<(i32 N)>;
def ICC_NE : ICC_VAL< 9>; // Not Equal
def ICC_E : ICC_VAL< 1>; // Equal
def ICC_G : ICC_VAL<10>; // Greater
def ICC_VC : ICC_VAL<15>; // Overflow Clear
def ICC_VS : ICC_VAL< 7>; // Overflow Set
-class FCC_VAL<int N> : PatLeaf<(i32 N)> {
- int FCCVal = N;
-}
+class FCC_VAL<int N> : PatLeaf<(i32 N)>;
def FCC_U : FCC_VAL<23>; // Unordered
def FCC_G : FCC_VAL<22>; // Greater
def FCC_UG : FCC_VAL<21>; // Unordered or Greater
// Pseudo instructions.
class Pseudo<dag ops, string asmstr, list<dag> pattern>
- : InstV8<ops, asmstr, pattern>;
+ : InstSP<ops, asmstr, pattern>;
def ADJCALLSTACKDOWN : Pseudo<(ops i32imm:$amt),
"!ADJCALLSTACKDOWN $amt",
// SELECT_CC_* - Used to implement the SELECT_CC DAG operation. Expanded by the
// scheduler into a branch sequence. This has to handle all permutations of
// selection between i32/f32/f64 on ICC and FCC.
-let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
+let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler.
def SELECT_CC_Int_ICC
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
"; SELECT_CC_Int_ICC PSEUDO!",
- [(set IntRegs:$dst, (V8selecticc IntRegs:$T, IntRegs:$F,
- imm:$Cond, ICC))]>;
+ [(set IntRegs:$dst, (SPselecticc IntRegs:$T, IntRegs:$F,
+ imm:$Cond))]>;
def SELECT_CC_Int_FCC
: Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, i32imm:$Cond),
"; SELECT_CC_Int_FCC PSEUDO!",
- [(set IntRegs:$dst, (V8selectfcc IntRegs:$T, IntRegs:$F,
- imm:$Cond, FCC))]>;
+ [(set IntRegs:$dst, (SPselectfcc IntRegs:$T, IntRegs:$F,
+ imm:$Cond))]>;
def SELECT_CC_FP_ICC
: Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
"; SELECT_CC_FP_ICC PSEUDO!",
- [(set FPRegs:$dst, (V8selecticc FPRegs:$T, FPRegs:$F,
- imm:$Cond, ICC))]>;
+ [(set FPRegs:$dst, (SPselecticc FPRegs:$T, FPRegs:$F,
+ imm:$Cond))]>;
def SELECT_CC_FP_FCC
: Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, i32imm:$Cond),
"; SELECT_CC_FP_FCC PSEUDO!",
- [(set FPRegs:$dst, (V8selectfcc FPRegs:$T, FPRegs:$F,
- imm:$Cond, FCC))]>;
+ [(set FPRegs:$dst, (SPselectfcc FPRegs:$T, FPRegs:$F,
+ imm:$Cond))]>;
def SELECT_CC_DFP_ICC
: Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
"; SELECT_CC_DFP_ICC PSEUDO!",
- [(set DFPRegs:$dst, (V8selecticc DFPRegs:$T, DFPRegs:$F,
- imm:$Cond, ICC))]>;
+ [(set DFPRegs:$dst, (SPselecticc DFPRegs:$T, DFPRegs:$F,
+ imm:$Cond))]>;
def SELECT_CC_DFP_FCC
: Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, i32imm:$Cond),
"; SELECT_CC_DFP_FCC PSEUDO!",
- [(set DFPRegs:$dst, (V8selectfcc DFPRegs:$T, DFPRegs:$F,
- imm:$Cond, FCC))]>;
+ [(set DFPRegs:$dst, (SPselectfcc DFPRegs:$T, DFPRegs:$F,
+ imm:$Cond))]>;
}
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
"add $b, $c, $dst",
[(set IntRegs:$dst, (add IntRegs:$b, simm13:$c))]>;
+
+// "LEA" forms of add (patterns to make tblgen happy)
+def LEA_ADDri : F3_2<2, 0b000000,
+ (ops IntRegs:$dst, MEMri:$addr),
+ "add ${addr:arith}, $dst",
+ [(set IntRegs:$dst, ADDRri:$addr)]>;
+
def ADDCCrr : F3_1<2, 0b010000,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "addcc $b, $c, $dst", []>;
+ "addcc $b, $c, $dst",
+ [(set IntRegs:$dst, (addc IntRegs:$b, IntRegs:$c))]>;
def ADDCCri : F3_2<2, 0b010000,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "addcc $b, $c, $dst", []>;
+ "addcc $b, $c, $dst",
+ [(set IntRegs:$dst, (addc IntRegs:$b, simm13:$c))]>;
def ADDXrr : F3_1<2, 0b001000,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "addx $b, $c, $dst", []>;
+ "addx $b, $c, $dst",
+ [(set IntRegs:$dst, (adde IntRegs:$b, IntRegs:$c))]>;
def ADDXri : F3_2<2, 0b001000,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "addx $b, $c, $dst", []>;
+ "addx $b, $c, $dst",
+ [(set IntRegs:$dst, (adde IntRegs:$b, simm13:$c))]>;
// Section B.15 - Subtract Instructions, p. 110
def SUBrr : F3_1<2, 0b000100,
[(set IntRegs:$dst, (sub IntRegs:$b, simm13:$c))]>;
def SUBXrr : F3_1<2, 0b001100,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
- "subx $b, $c, $dst", []>;
+ "subx $b, $c, $dst",
+ [(set IntRegs:$dst, (sube IntRegs:$b, IntRegs:$c))]>;
def SUBXri : F3_2<2, 0b001100,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
- "subx $b, $c, $dst", []>;
+ "subx $b, $c, $dst",
+ [(set IntRegs:$dst, (sube IntRegs:$b, simm13:$c))]>;
def SUBCCrr : F3_1<2, 0b010100,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
"subcc $b, $c, $dst",
- [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, IntRegs:$c))]>;
+ [(set IntRegs:$dst, (SPcmpicc IntRegs:$b, IntRegs:$c))]>;
def SUBCCri : F3_2<2, 0b010100,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
"subcc $b, $c, $dst",
- [(set IntRegs:$dst, (V8cmpicc IntRegs:$b, simm13:$c))]>;
+ [(set IntRegs:$dst, (SPcmpicc IntRegs:$b, simm13:$c))]>;
def SUBXCCrr: F3_1<2, 0b011100,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
"subxcc $b, $c, $dst", []>;
def UMULri : F3_2<2, 0b001010,
(ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
"umul $b, $c, $dst", []>;
+
def SMULrr : F3_1<2, 0b001011,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
"smul $b, $c, $dst",
"smul $b, $c, $dst",
[(set IntRegs:$dst, (mul IntRegs:$b, simm13:$c))]>;
+/*
+//===-------------------------
+// Sparc Example
+defm intinst{OPC1, OPC2}<bits Opc, string asmstr, SDNode code> {
+ def OPC1 : F3_1<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
+ [(set IntRegs:$dst, (code IntRegs:$b, IntRegs:$c))]>;
+ def OPC2 : F3_2<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+ [(set IntRegs:$dst, (code IntRegs:$b, simm13:$c))]>;
+}
+defm intinst_np{OPC1, OPC2}<bits Opc, string asmstr> {
+ def OPC1 : F3_1<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
+ []>;
+ def OPC2 : F3_2<2, Opc, asmstr, (ops IntRegs:$dst, IntRegs:$b, i32imm:$c),
+ []>;
+}
+
+def { ADDXrr, ADDXri} : intinstnp<0b001000, "addx $b, $c, $dst">;
+def { SUBrr, SUBri} : intinst <0b000100, "sub $b, $c, $dst", sub>;
+def intinstnp{ SUBXrr, SUBXri}<0b001100, "subx $b, $c, $dst">;
+def intinst {SUBCCrr, SUBCCri}<0b010100, "subcc $b, $c, $dst", SPcmpicc>;
+def intinst { SMULrr, SMULri}<0b001011, "smul $b, $c, $dst", mul>;
+
+//===-------------------------
+// X86 Example
+defm cmov32<id OPC1, id OPC2, int opc, string asmstr, PatLeaf cond> {
+ def OPC1 : I<opc, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2),
+ asmstr+" {$src2, $dst|$dst, $src2}",
+ [(set R32:$dst, (X86cmov R32:$src1, R32:$src2, cond))]>, TB;
+ def OPC2 : I<opc, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2),
+ asmstr+" {$src2, $dst|$dst, $src2}",
+ [(set R32:$dst, (X86cmov R32:$src1,
+ (loadi32 addr:$src2), cond))]>, TB;
+}
+
+def cmov<CMOVL32rr, CMOVL32rm, 0x4C, "cmovl", X86_COND_L>;
+def cmov<CMOVB32rr, CMOVB32rm, 0x4C, "cmovb", X86_COND_B>;
+
+//===-------------------------
+// PPC Example
+
+def fpunop<id OPC1, id OPC2, id FORM, int op1, int op2, int op3, string asmstr,
+ SDNode code> {
+ def OPC1 : FORM<op1, op3, (ops F4RC:$frD, F4RC:$frB),
+ asmstr+" $frD, $frB", FPGeneral,
+ [(set F4RC:$frD, (code F4RC:$frB))]>;
+ def OPC2 : FORM<op2, op3, (ops F8RC:$frD, F8RC:$frB),
+ asmstr+" $frD, $frB", FPGeneral,
+ [(set F8RC:$frD, (code F8RC:$frB))]>;
+}
+
+def fpunop< FABSS, FABSD, XForm_26, 63, 63, 264, "fabs", fabs>;
+def fpunop<FNABSS, FNABSD, XForm_26, 63, 63, 136, "fnabs", fnabs>;
+def fpunop< FNEGS, FNEGD, XForm_26, 63, 63, 40, "fneg", fneg>;
+*/
+
// Section B.19 - Divide Instructions, p. 115
def UDIVrr : F3_1<2, 0b001110,
(ops IntRegs:$dst, IntRegs:$b, IntRegs:$c),
// Section B.21 - Branch on Integer Condition Codes Instructions, p. 119
// conditional branch class:
-class BranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
+class BranchSP<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
: F2_2<cc, 0b010, ops, asmstr, pattern> {
let isBranch = 1;
let isTerminator = 1;
}
let isBarrier = 1 in
- def BA : BranchV8<0b1000, (ops brtarget:$dst),
+ def BA : BranchSP<0b1000, (ops brtarget:$dst),
"ba $dst",
[(br bb:$dst)]>;
-def BNE : BranchV8<0b1001, (ops brtarget:$dst),
- "bne $dst",
- [(V8bricc bb:$dst, ICC_NE, ICC)]>;
-def BE : BranchV8<0b0001, (ops brtarget:$dst),
- "be $dst",
- [(V8bricc bb:$dst, ICC_E, ICC)]>;
-def BG : BranchV8<0b1010, (ops brtarget:$dst),
- "bg $dst",
- [(V8bricc bb:$dst, ICC_G, ICC)]>;
-def BLE : BranchV8<0b0010, (ops brtarget:$dst),
- "ble $dst",
- [(V8bricc bb:$dst, ICC_LE, ICC)]>;
-def BGE : BranchV8<0b1011, (ops brtarget:$dst),
- "bge $dst",
- [(V8bricc bb:$dst, ICC_GE, ICC)]>;
-def BL : BranchV8<0b0011, (ops brtarget:$dst),
- "bl $dst",
- [(V8bricc bb:$dst, ICC_L, ICC)]>;
-def BGU : BranchV8<0b1100, (ops brtarget:$dst),
- "bgu $dst",
- [(V8bricc bb:$dst, ICC_GU, ICC)]>;
-def BLEU : BranchV8<0b0100, (ops brtarget:$dst),
- "bleu $dst",
- [(V8bricc bb:$dst, ICC_LEU, ICC)]>;
-def BCC : BranchV8<0b1101, (ops brtarget:$dst),
- "bcc $dst",
- [(V8bricc bb:$dst, ICC_CC, ICC)]>;
-def BCS : BranchV8<0b0101, (ops brtarget:$dst),
- "bcs $dst",
- [(V8bricc bb:$dst, ICC_CS, ICC)]>;
-def BPOS : BranchV8<0b1110, (ops brtarget:$dst),
- "bpos $dst",
- [(V8bricc bb:$dst, ICC_POS, ICC)]>;
-def BNEG : BranchV8<0b0110, (ops brtarget:$dst),
- "bneg $dst",
- [(V8bricc bb:$dst, ICC_NEG, ICC)]>;
-def BVC : BranchV8<0b1111, (ops brtarget:$dst),
- "bvc $dst",
- [(V8bricc bb:$dst, ICC_VC, ICC)]>;
-def BVS : BranchV8<0b0111, (ops brtarget:$dst),
- "bvs $dst",
- [(V8bricc bb:$dst, ICC_VS, ICC)]>;
-
+
+// FIXME: the encoding for the JIT should look at the condition field.
+def BCOND : BranchSP<0, (ops brtarget:$dst, CCOp:$cc),
+ "b$cc $dst",
+ [(SPbricc bb:$dst, imm:$cc)]>;
// Section B.22 - Branch on Floating-point Condition Codes Instructions, p. 121
// floating-point conditional branch class:
-class FPBranchV8<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
+class FPBranchSP<bits<4> cc, dag ops, string asmstr, list<dag> pattern>
: F2_2<cc, 0b110, ops, asmstr, pattern> {
let isBranch = 1;
let isTerminator = 1;
let noResults = 1;
}
-def FBU : FPBranchV8<0b0111, (ops brtarget:$dst),
- "fbu $dst",
- [(V8brfcc bb:$dst, FCC_U, FCC)]>;
-def FBG : FPBranchV8<0b0110, (ops brtarget:$dst),
- "fbg $dst",
- [(V8brfcc bb:$dst, FCC_G, FCC)]>;
-def FBUG : FPBranchV8<0b0101, (ops brtarget:$dst),
- "fbug $dst",
- [(V8brfcc bb:$dst, FCC_UG, FCC)]>;
-def FBL : FPBranchV8<0b0100, (ops brtarget:$dst),
- "fbl $dst",
- [(V8brfcc bb:$dst, FCC_L, FCC)]>;
-def FBUL : FPBranchV8<0b0011, (ops brtarget:$dst),
- "fbul $dst",
- [(V8brfcc bb:$dst, FCC_UL, FCC)]>;
-def FBLG : FPBranchV8<0b0010, (ops brtarget:$dst),
- "fblg $dst",
- [(V8brfcc bb:$dst, FCC_LG, FCC)]>;
-def FBNE : FPBranchV8<0b0001, (ops brtarget:$dst),
- "fbne $dst",
- [(V8brfcc bb:$dst, FCC_NE, FCC)]>;
-def FBE : FPBranchV8<0b1001, (ops brtarget:$dst),
- "fbe $dst",
- [(V8brfcc bb:$dst, FCC_E, FCC)]>;
-def FBUE : FPBranchV8<0b1010, (ops brtarget:$dst),
- "fbue $dst",
- [(V8brfcc bb:$dst, FCC_UE, FCC)]>;
-def FBGE : FPBranchV8<0b1011, (ops brtarget:$dst),
- "fbge $dst",
- [(V8brfcc bb:$dst, FCC_GE, FCC)]>;
-def FBUGE: FPBranchV8<0b1100, (ops brtarget:$dst),
- "fbuge $dst",
- [(V8brfcc bb:$dst, FCC_UGE, FCC)]>;
-def FBLE : FPBranchV8<0b1101, (ops brtarget:$dst),
- "fble $dst",
- [(V8brfcc bb:$dst, FCC_LE, FCC)]>;
-def FBULE: FPBranchV8<0b1110, (ops brtarget:$dst),
- "fbule $dst",
- [(V8brfcc bb:$dst, FCC_ULE, FCC)]>;
-def FBO : FPBranchV8<0b1111, (ops brtarget:$dst),
- "fbo $dst",
- [(V8brfcc bb:$dst, FCC_O, FCC)]>;
-
+// FIXME: the encoding for the JIT should look at the condition field.
+def FBCOND : FPBranchSP<0, (ops brtarget:$dst, CCOp:$cc),
+ "fb$cc $dst",
+ [(SPbrfcc bb:$dst, imm:$cc)]>;
// Section B.24 - Call and Link Instruction, p. 125
hasDelaySlot = 1, isCall = 1, noResults = 1,
Defs = [O0, O1, O2, O3, O4, O5, O7, G1, G2, G3, G4, G5, G6, G7,
D0, D1, D2, D3, D4, D5, D6, D7, D8, D9, D10, D11, D12, D13, D14, D15] in {
- def CALL : InstV8<(ops calltarget:$dst),
+ def CALL : InstSP<(ops calltarget:$dst),
"call $dst", []> {
bits<30> disp;
let op = 1;
def FITOS : F3_3<2, 0b110100, 0b011000100,
(ops FPRegs:$dst, FPRegs:$src),
"fitos $src, $dst",
- [(set FPRegs:$dst, (V8itof FPRegs:$src))]>;
+ [(set FPRegs:$dst, (SPitof FPRegs:$src))]>;
def FITOD : F3_3<2, 0b110100, 0b011001000,
(ops DFPRegs:$dst, FPRegs:$src),
"fitod $src, $dst",
- [(set DFPRegs:$dst, (V8itof FPRegs:$src))]>;
+ [(set DFPRegs:$dst, (SPitof FPRegs:$src))]>;
// Convert Floating-point to Integer Instructions, p. 142
def FSTOI : F3_3<2, 0b110100, 0b011010001,
(ops FPRegs:$dst, FPRegs:$src),
"fstoi $src, $dst",
- [(set FPRegs:$dst, (V8ftoi FPRegs:$src))]>;
+ [(set FPRegs:$dst, (SPftoi FPRegs:$src))]>;
def FDTOI : F3_3<2, 0b110100, 0b011010010,
(ops FPRegs:$dst, DFPRegs:$src),
"fdtoi $src, $dst",
- [(set FPRegs:$dst, (V8ftoi DFPRegs:$src))]>;
+ [(set FPRegs:$dst, (SPftoi DFPRegs:$src))]>;
// Convert between Floating-point Formats Instructions, p. 143
def FSTOD : F3_3<2, 0b110100, 0b011001001,
def FCMPS : F3_3<2, 0b110101, 0b001010001,
(ops FPRegs:$src1, FPRegs:$src2),
"fcmps $src1, $src2\n\tnop",
- [(set FCC, (V8cmpfcc FPRegs:$src1, FPRegs:$src2))]>;
+ [(SPcmpfcc FPRegs:$src1, FPRegs:$src2)]>;
def FCMPD : F3_3<2, 0b110101, 0b001010010,
(ops DFPRegs:$src1, DFPRegs:$src2),
"fcmpd $src1, $src2\n\tnop",
- [(set FCC, (V8cmpfcc DFPRegs:$src1, DFPRegs:$src2))]>;
+ [(SPcmpfcc DFPRegs:$src1, DFPRegs:$src2)]>;
//===----------------------------------------------------------------------===//
// V9 Conditional Moves.
let Predicates = [HasV9], isTwoAddress = 1 in {
+ // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
// FIXME: Add instruction encodings for the JIT some day.
- class IntCMOVICCrr<string asmstr, ICC_VAL CC>
- : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
- asmstr,
+ def MOVICCrr
+ : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, CCOp:$cc),
+ "mov$cc %icc, $F, $dst",
[(set IntRegs:$dst,
- (V8selecticc IntRegs:$F, IntRegs:$T, CC, ICC))]> {
- int CondBits = CC.ICCVal;
- }
-
-
- // Move Integer Register on Condition (MOVcc) p. 194 of the V9 manual.
- def MOVNErr : IntCMOVICCrr< "movne %icc, $F, $dst", ICC_NE>;
- def MOVErr : IntCMOVICCrr< "move %icc, $F, $dst", ICC_E>;
- def MOVGrr : IntCMOVICCrr< "movg %icc, $F, $dst", ICC_G>;
- def MOVLErr : IntCMOVICCrr< "movle %icc, $F, $dst", ICC_LE>;
- def MOVGErr : IntCMOVICCrr< "movge %icc, $F, $dst", ICC_GE>;
- def MOVLrr : IntCMOVICCrr< "movl %icc, $F, $dst", ICC_L>;
- def MOVGUrr : IntCMOVICCrr< "movgu %icc, $F, $dst", ICC_GU>;
- def MOVLEUrr : IntCMOVICCrr<"movleu %icc, $F, $dst", ICC_LEU>;
- def MOVCCrr : IntCMOVICCrr< "movcc %icc, $F, $dst", ICC_CC>;
- def MOVCSrr : IntCMOVICCrr< "movcs %icc, $F, $dst", ICC_CS>;
- def MOVPOSrr : IntCMOVICCrr<"movpos %icc, $F, $dst", ICC_POS>;
- def MOVNEGrr : IntCMOVICCrr<"movneg %icc, $F, $dst", ICC_NEG>;
- def MOVVCrr : IntCMOVICCrr< "movvc %icc, $F, $dst", ICC_VC>;
- def MOVVSrr : IntCMOVICCrr< "movvs %icc, $F, $dst", ICC_VS>;
-
- // FIXME: Allow regalloc of the fcc condition code some day.
- class IntCMOVFCCrr<string asmstr, FCC_VAL CC>
- : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F),
- asmstr,
+ (SPselecticc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
+ def MOVICCri
+ : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, CCOp:$cc),
+ "mov$cc %icc, $F, $dst",
[(set IntRegs:$dst,
- (V8selectfcc IntRegs:$F, IntRegs:$T, CC, FCC))]> {
- int CondBits = CC.FCCVal;
- }
+ (SPselecticc simm11:$F, IntRegs:$T, imm:$cc))]>;
+
+ def MOVFCCrr
+ : Pseudo<(ops IntRegs:$dst, IntRegs:$T, IntRegs:$F, CCOp:$cc),
+ "mov$cc %fcc0, $F, $dst",
+ [(set IntRegs:$dst,
+ (SPselectfcc IntRegs:$F, IntRegs:$T, imm:$cc))]>;
+ def MOVFCCri
+ : Pseudo<(ops IntRegs:$dst, IntRegs:$T, i32imm:$F, CCOp:$cc),
+ "mov$cc %fcc0, $F, $dst",
+ [(set IntRegs:$dst,
+ (SPselectfcc simm11:$F, IntRegs:$T, imm:$cc))]>;
+
+ def FMOVS_ICC
+ : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, CCOp:$cc),
+ "fmovs$cc %icc, $F, $dst",
+ [(set FPRegs:$dst,
+ (SPselecticc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
+ def FMOVD_ICC
+ : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
+ "fmovd$cc %icc, $F, $dst",
+ [(set DFPRegs:$dst,
+ (SPselecticc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
+ def FMOVS_FCC
+ : Pseudo<(ops FPRegs:$dst, FPRegs:$T, FPRegs:$F, CCOp:$cc),
+ "fmovs$cc %fcc0, $F, $dst",
+ [(set FPRegs:$dst,
+ (SPselectfcc FPRegs:$F, FPRegs:$T, imm:$cc))]>;
+ def FMOVD_FCC
+ : Pseudo<(ops DFPRegs:$dst, DFPRegs:$T, DFPRegs:$F, CCOp:$cc),
+ "fmovd$cc %fcc0, $F, $dst",
+ [(set DFPRegs:$dst,
+ (SPselectfcc DFPRegs:$F, DFPRegs:$T, imm:$cc))]>;
- def MOVFUrr : IntCMOVFCCrr< "movfu %fcc, $F, $dst", FCC_U>;
- def MOVFGrr : IntCMOVFCCrr< "movfg %fcc, $F, $dst", FCC_G>;
- def MOVFUGrr : IntCMOVFCCrr< "movfug %fcc, $F, $dst", FCC_UG>;
- def MOVFLrr : IntCMOVFCCrr< "movfl %fcc, $F, $dst", FCC_L>;
- def MOVFULrr : IntCMOVFCCrr< "movful %fcc, $F, $dst", FCC_UL>;
- def MOVFLGrr : IntCMOVFCCrr< "movflg %fcc, $F, $dst", FCC_LG>;
- def MOVFNErr : IntCMOVFCCrr< "movfne %fcc, $F, $dst", FCC_NE>;
- def MOVFErr : IntCMOVFCCrr< "movfe %fcc, $F, $dst", FCC_E>;
- def MOVFUErr : IntCMOVFCCrr< "movfue %fcc, $F, $dst", FCC_UE>;
- def MOVFGErr : IntCMOVFCCrr< "movfge %fcc, $F, $dst", FCC_GE>;
- def MOVFUGErr : IntCMOVFCCrr<"movfuge %fcc, $F, $dst", FCC_UGE>;
- def MOVFLErr : IntCMOVFCCrr< "movfle %fcc, $F, $dst", FCC_LE>;
- def MOVFULErr : IntCMOVFCCrr<"movfule %fcc, $F, $dst", FCC_ULE>;
- def MOVFOrr : IntCMOVFCCrr< "movfo %fcc, $F, $dst", FCC_O>;
}
// Floating-Point Move Instructions, p. 164 of the V9 manual.
def : Pat<(i32 imm:$val),
(ORri (SETHIi (HI22 imm:$val)), (LO10 imm:$val))>;
+// subc
+def : Pat<(subc IntRegs:$b, IntRegs:$c),
+ (SUBCCrr IntRegs:$b, IntRegs:$c)>;
+def : Pat<(subc IntRegs:$b, simm13:$val),
+ (SUBCCri IntRegs:$b, imm:$val)>;
+
// Global addresses, constant pool entries
-def : Pat<(V8hi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
-def : Pat<(V8lo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
-def : Pat<(V8hi tconstpool:$in), (SETHIi tconstpool:$in)>;
-def : Pat<(V8lo tconstpool:$in), (ORri G0, tconstpool:$in)>;
+def : Pat<(SPhi tglobaladdr:$in), (SETHIi tglobaladdr:$in)>;
+def : Pat<(SPlo tglobaladdr:$in), (ORri G0, tglobaladdr:$in)>;
+def : Pat<(SPhi tconstpool:$in), (SETHIi tconstpool:$in)>;
+def : Pat<(SPlo tconstpool:$in), (ORri G0, tconstpool:$in)>;
// Add reg, lo. This is used when taking the addr of a global/constpool entry.
-def : Pat<(add IntRegs:$r, (V8lo tglobaladdr:$in)),
+def : Pat<(add IntRegs:$r, (SPlo tglobaladdr:$in)),
(ADDri IntRegs:$r, tglobaladdr:$in)>;
-def : Pat<(add IntRegs:$r, (V8lo tconstpool:$in)),
+def : Pat<(add IntRegs:$r, (SPlo tconstpool:$in)),
(ADDri IntRegs:$r, tconstpool:$in)>;
-
// Calls:
def : Pat<(call tglobaladdr:$dst),
(CALL tglobaladdr:$dst)>;
-def : Pat<(call externalsym:$dst),
- (CALL externalsym:$dst)>;
+def : Pat<(call texternalsym:$dst),
+ (CALL texternalsym:$dst)>;
def : Pat<(ret), (RETL)>;
projects / oota-llvm.git / blobdiff