return 0;
}
+const unsigned* SparcRegisterInfo::getCalleeSaveRegs() const {
+ static const unsigned CalleeSaveRegs[] = { 0 };
+ return CalleeSaveRegs;
+}
+
+const TargetRegisterClass* const*
+SparcRegisterInfo::getCalleeSaveRegClasses() const {
+ static const TargetRegisterClass * const CalleeSaveRegClasses[] = { 0 };
+ return CalleeSaveRegClasses;
+}
+
+
void SparcRegisterInfo::
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
MachineBasicBlock::iterator I) const {
if (MI.getOpcode() == SP::ADJCALLSTACKDOWN)
Size = -Size;
if (Size)
- BuildMI(MBB, I, SP::ADDri, 2, SP::O6).addReg(SP::O6).addSImm(Size);
+ BuildMI(MBB, I, SP::ADDri, 2, SP::O6).addReg(SP::O6).addImm(Size);
MBB.erase(I);
}
if (Offset >= -4096 && Offset <= 4095) {
// If the offset is small enough to fit in the immediate field, directly
// encode it.
- MI.SetMachineOperandReg(i, SP::I6);
- MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed,Offset);
+ MI.getOperand(i).ChangeToRegister(SP::I6, false);
+ MI.getOperand(i+1).ChangeToImmediate(Offset);
} else {
// Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
// scavenge a register here instead of reserving G1 all of the time.
BuildMI(*MI.getParent(), II, SP::ADDrr, 2,
SP::G1).addReg(SP::G1).addReg(SP::I6);
// Insert: G1+%lo(offset) into the user.
- MI.SetMachineOperandReg(i, SP::G1);
- MI.SetMachineOperandConst(i+1, MachineOperand::MO_SignExtendedImmed,
- Offset & ((1 << 10)-1));
+ MI.getOperand(i).ChangeToRegister(SP::G1, false);
+ MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
}
}
BuildMI(MBB, MBBI, SP::RESTORErr, 2, SP::G0).addReg(SP::G0).addReg(SP::G0);
}
-void SparcRegisterInfo::getLocation(MachineFunction &MF, unsigned Index,
- MachineLocation &ML) const {
- assert(0 && "Needs to be defined for target");
- MachineFrameInfo *MFI = MF.getFrameInfo();
-
- // FIXME - Needs to handle register variables.
- // FIXME - Faking that llvm number is same as gcc numbering.
- ML.set(SP::G1 - SP::G0,
- MFI->getObjectOffset(Index) + MFI->getStackSize());
+unsigned SparcRegisterInfo::getRARegister() const {
+ assert(0 && "What is the return address register");
+ return 0;
+}
+
+unsigned SparcRegisterInfo::getFrameRegister(MachineFunction &MF) const {
+ assert(0 && "What is the frame register");
+ return SP::G1;
}
#include "SparcGenRegisterInfo.inc"