fix the X86 backend to just drop llvm.declare nodes for VLAs instead of

[oota-llvm.git] / lib / Target / Sparc / SparcRegisterInfo.cpp

diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp
index cd50ad1dc1fee15b7d8a0e0d138bbdab2a189154..94853a656f79ca6bb76c3d285b4ac84224b1639b 100644 (file)
--- a/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -30,15 +30,6 @@ SparcRegisterInfo::SparcRegisterInfo(SparcSubtarget &st,
     Subtarget(st), TII(tii) {
 }
 
-void SparcRegisterInfo::reMaterialize(MachineBasicBlock &MBB,
-                                      MachineBasicBlock::iterator I,
-                                      unsigned DestReg,
-                                      const MachineInstr *Orig) const {
-  MachineInstr *MI = Orig->clone();
-  MI->getOperand(0).setReg(DestReg);
-  MBB.insert(I, MI);
-}
-
 const unsigned* SparcRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF)
                                                                          const {
   static const unsigned CalleeSavedRegs[] = { 0 };
@@ -89,7 +80,7 @@ void SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
 
   unsigned i = 0;
   MachineInstr &MI = *II;
-  while (!MI.getOperand(i).isFrameIndex()) {
+  while (!MI.getOperand(i).isFI()) {
     ++i;
     assert(i < MI.getNumOperands() && "Instr doesn't have FrameIndex operand!");
   }
@@ -146,7 +137,7 @@ void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
   
   if (NumBytes >= -4096) {
     BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri),
-            SP::O6).addImm(NumBytes).addReg(SP::O6);
+            SP::O6).addReg(SP::O6).addImm(NumBytes);
   } else {
     MachineBasicBlock::iterator InsertPt = MBB.begin();
     // Emit this the hard way.  This clobbers G1 which we always know is