[MC] Require an MCContext when constructing an MCDisassembler.

[oota-llvm.git] / lib / Target / Sparc / SparcTargetMachine.cpp

diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp
index 654b6255000a7b9d48829afbc1b5e2754f9991f0..83f3474759b62d7719191400c3cdb766a1cac360 100644 (file)
--- a/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -25,23 +25,26 @@ extern "C" void LLVMInitializeSparcTarget() {
 
 static std::string computeDataLayout(const SparcSubtarget &ST) {
   // Sparc is big endian.
-  std::string Ret = "E";
+  std::string Ret = "E-m:e";
 
-  // V9 has 64 bit pointers, others have 32bit pointers.
-  if (ST.is64Bit())
-    Ret += "-p:64:64:64";
-  else
-    Ret += "-p:32:32:32";
+  // Some ABIs have 32bit pointers.
+  if (!ST.is64Bit())
+    Ret += "-p:32:32";
 
-  // Alignments for 64 bit integers and doubles.
-  Ret += "-i64:64:64-f64:64:64";
+  // Alignments for 64 bit integers.
+  Ret += "-i64:64";
 
   // On SparcV9 128 floats are aligned to 128 bits, on others only to 64.
   // On SparcV9 registers can hold 64 or 32 bits, on others only 32.
   if (ST.is64Bit())
-    Ret += "-f128:128:128-n32:64";
+    Ret += "-n32:64";
+  else
+    Ret += "-f128:64-n32";
+
+  if (ST.is64Bit())
+    Ret += "-S128";
   else
-    Ret += "-f128:64:64-n32";
+    Ret += "-S64";
 
   return Ret;
 }