For PR786:

[oota-llvm.git] / lib / Target / Sparc / SparcTargetMachine.cpp

diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp
index 88f88f4acdee8f49a758fd14a4cefafc4f7a2cbc..98912a2353127e578281e2c466628e7f48539b4b 100644 (file)
--- a/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -1,4 +1,4 @@
-//===-- SparcV8TargetMachine.cpp - Define TargetMachine for SparcV8 -------===//
+//===-- SparcTargetMachine.cpp - Define TargetMachine for Sparc -----------===//
 //
 //                     The LLVM Compiler Infrastructure
 //
@@ -10,36 +10,33 @@
 //
 //===----------------------------------------------------------------------===//
 
-#include "SparcV8TargetMachine.h"
-#include "SparcV8.h"
-#include "llvm/Assembly/PrintModulePass.h"
+#include "SparcTargetAsmInfo.h"
+#include "SparcTargetMachine.h"
+#include "Sparc.h"
 #include "llvm/Module.h"
 #include "llvm/PassManager.h"
-#include "llvm/CodeGen/MachineFunction.h"
-#include "llvm/CodeGen/Passes.h"
-#include "llvm/Target/TargetOptions.h"
 #include "llvm/Target/TargetMachineRegistry.h"
-#include "llvm/Transforms/Scalar.h"
-#include "llvm/Support/CommandLine.h"
 #include <iostream>
 using namespace llvm;
 
 namespace {
   // Register the target.
-  RegisterTarget<SparcV8TargetMachine> X("sparcv8","  SPARC V8 (experimental)");
+  RegisterTarget<SparcTargetMachine> X("sparc", "  SPARC");
 }
 
-/// SparcV8TargetMachine ctor - Create an ILP32 architecture model
+const TargetAsmInfo *SparcTargetMachine::createTargetAsmInfo() const {
+  return new SparcTargetAsmInfo(*this);
+}
+
+/// SparcTargetMachine ctor - Create an ILP32 architecture model
 ///
-SparcV8TargetMachine::SparcV8TargetMachine(const Module &M,
-                                           IntrinsicLowering *IL,
-                                           const std::string &FS)
-  : TargetMachine("SparcV8", IL, false, 4, 4),
-    Subtarget(M, FS),
+SparcTargetMachine::SparcTargetMachine(const Module &M, const std::string &FS)
+  : DataLayout("E-p:32:32"),
+    Subtarget(M, FS), InstrInfo(Subtarget),
     FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0) {
 }
 
-unsigned SparcV8TargetMachine::getModuleMatchQuality(const Module &M) {
+unsigned SparcTargetMachine::getModuleMatchQuality(const Module &M) {
   std::string TT = M.getTargetTriple();
   if (TT.size() >= 6 && std::string(TT.begin(), TT.begin()+6) == "sparc-")
     return 20;
@@ -47,7 +44,7 @@ unsigned SparcV8TargetMachine::getModuleMatchQuality(const Module &M) {
   if (M.getEndianness()  == Module::BigEndian &&
       M.getPointerSize() == Module::Pointer32)
 #ifdef __sparc__
-    return 20;   // BE/32 ==> Prefer sparcv8 on sparc
+    return 20;   // BE/32 ==> Prefer sparc on sparc
 #else
     return 5;    // BE/32 ==> Prefer ppc elsewhere
 #endif
@@ -58,58 +55,23 @@ unsigned SparcV8TargetMachine::getModuleMatchQuality(const Module &M) {
   return 0;
 }
 
-/// addPassesToEmitFile - Add passes to the specified pass manager
-/// to implement a static compiler for this target.
-///
-bool SparcV8TargetMachine::addPassesToEmitFile(PassManager &PM,
-                                               std::ostream &Out,
-                                               CodeGenFileType FileType,
-                                               bool Fast) {
-  if (FileType != TargetMachine::AssemblyFile) return true;
-
-  // FIXME: Implement efficient support for garbage collection intrinsics.
-  PM.add(createLowerGCPass());
-
-  // FIXME: implement the invoke/unwind instructions!
-  PM.add(createLowerInvokePass());
-
-  // FIXME: implement the switch instruction in the instruction selector.
-  PM.add(createLowerSwitchPass());
-
-  // Print LLVM code input to instruction selector:
-  if (PrintMachineCode)
-    PM.add(new PrintFunctionPass());
-
-  // Make sure that no unreachable blocks are instruction selected.
-  PM.add(createUnreachableBlockEliminationPass());
-  
-  PM.add(createSparcV8ISelDag(*this));
-
-  // Print machine instructions as they were initially generated.
-  if (PrintMachineCode)
-    PM.add(createMachineFunctionPrinterPass(&std::cerr));
-
-  PM.add(createRegisterAllocator());
-  PM.add(createPrologEpilogCodeInserter());
-
-  // Print machine instructions after register allocation and prolog/epilog
-  // insertion.
-  if (PrintMachineCode)
-    PM.add(createMachineFunctionPrinterPass(&std::cerr));
-
-  PM.add(createSparcV8FPMoverPass(*this));
-
-  PM.add(createSparcV8DelaySlotFillerPass(*this));
+bool SparcTargetMachine::addInstSelector(FunctionPassManager &PM, bool Fast) {
+  PM.add(createSparcISelDag(*this));
+  return false;
+}
 
-  // Print machine instructions after filling delay slots.
-  if (PrintMachineCode)
-    PM.add(createMachineFunctionPrinterPass(&std::cerr));
+/// addPreEmitPass - This pass may be implemented by targets that want to run
+/// passes immediately before machine code is emitted.  This should return
+/// true if -print-machineinstrs should print out the code after the passes.
+bool SparcTargetMachine::addPreEmitPass(FunctionPassManager &PM, bool Fast) {
+  PM.add(createSparcFPMoverPass(*this));
+  PM.add(createSparcDelaySlotFillerPass(*this));
+  return true;
+}
 
+bool SparcTargetMachine::addAssemblyEmitter(FunctionPassManager &PM, bool Fast, 
+                                            std::ostream &Out) {
   // Output assembly language.
-  PM.add(createSparcV8CodePrinterPass(Out, *this));
-
-  // Delete the MachineInstrs we generated, since they're no longer needed.
-  PM.add(createMachineCodeDeleter());
+  PM.add(createSparcCodePrinterPass(Out, *this));
   return false;
 }
-