Add FSTOI, FDTOI (fp to integer cast) instructions.

[oota-llvm.git] / lib / Target / Sparc / SparcTargetMachine.cpp

diff --git a/lib/Target/Sparc/SparcTargetMachine.cpp b/lib/Target/Sparc/SparcTargetMachine.cpp
index f9a499dca43f8a7ac77ce6a609162bb2abd65632..a6b69d62633c2479830d9e6cb6fc84a8684c4031 100644 (file)
--- a/lib/Target/Sparc/SparcTargetMachine.cpp
+++ b/lib/Target/Sparc/SparcTargetMachine.cpp
@@ -14,25 +14,44 @@
 #include "SparcV8.h"
 #include "llvm/Module.h"
 #include "llvm/PassManager.h"
-#include "llvm/Target/TargetMachineImpls.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/Passes.h"
+#include "llvm/Target/TargetOptions.h"
+#include "llvm/Target/TargetMachineRegistry.h"
+#include "llvm/Transforms/Scalar.h"
+#include <iostream>
 using namespace llvm;
 
-// allocateSparcV8TargetMachine - Allocate and return a subclass of 
-// TargetMachine that implements the SparcV8 backend.
-//
-TargetMachine *llvm::allocateSparcV8TargetMachine(const Module &M,
-                                                  IntrinsicLowering *IL) {
-  return new SparcV8TargetMachine(M, IL);
+namespace {
+  // Register the target.
+  RegisterTarget<SparcV8TargetMachine> X("sparcv8","  SPARC V8 (experimental)");
 }
 
 /// SparcV8TargetMachine ctor - Create an ILP32 architecture model
 ///
 SparcV8TargetMachine::SparcV8TargetMachine(const Module &M,
                                            IntrinsicLowering *IL)
-  : TargetMachine("SparcV8", IL, true, 4, 4, 4, 4, 4),
-    FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 4), JITInfo(*this) {
+  : TargetMachine("SparcV8", IL, false, 4, 4, 8, 4, 8),
+    FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 0), JITInfo(*this) {
+}
+
+unsigned SparcV8TargetMachine::getJITMatchQuality() {
+  return 0; // No JIT yet.
+}
+
+unsigned SparcV8TargetMachine::getModuleMatchQuality(const Module &M) {
+  if (M.getEndianness()  == Module::BigEndian &&
+      M.getPointerSize() == Module::Pointer32)
+#ifdef __sparc__
+    return 20;   // BE/32 ==> Prefer sparcv8 on sparc
+#else
+    return 5;    // BE/32 ==> Prefer ppc elsewhere
+#endif
+  else if (M.getEndianness() != Module::AnyEndianness ||
+           M.getPointerSize() != Module::AnyPointerSize)
+    return 0;                                    // Match for some other target
+
+  return getJITMatchQuality()/2;
 }
 
 /// addPassesToEmitAssembly - Add passes to the specified pass manager
@@ -40,19 +59,51 @@ SparcV8TargetMachine::SparcV8TargetMachine(const Module &M,
 ///
 bool SparcV8TargetMachine::addPassesToEmitAssembly(PassManager &PM,
                                               std::ostream &Out) {
+  // FIXME: Implement efficient support for garbage collection intrinsics.
+  PM.add(createLowerGCPass());
+
+  // Replace malloc and free instructions with library calls.
+  PM.add(createLowerAllocationsPass());
+
+  // FIXME: implement the select instruction in the instruction selector.
+  PM.add(createLowerSelectPass());
+  
+  // FIXME: implement the switch instruction in the instruction selector.
+  PM.add(createLowerSwitchPass());
+
+  // FIXME: implement the invoke/unwind instructions!
+  PM.add(createLowerInvokePass());
+
+  PM.add(createLowerConstantExpressionsPass());
+
+  // Make sure that no unreachable blocks are instruction selected.
+  PM.add(createUnreachableBlockEliminationPass());
+
   PM.add(createSparcV8SimpleInstructionSelector(*this));
 
-  // Print machine instructions as they are created.
-  PM.add(createMachineFunctionPrinterPass(&std::cerr));
+  // Print machine instructions as they were initially generated.
+  if (PrintMachineCode)
+    PM.add(createMachineFunctionPrinterPass(&std::cerr));
 
   PM.add(createRegisterAllocator());
   PM.add(createPrologEpilogCodeInserter());
-  // <insert assembly code output passes here>
 
-  // This is not a correct asm writer by any means, but at least we see what we
-  // are producing.
-  PM.add(createMachineFunctionPrinterPass(&Out));
+  // Print machine instructions after register allocation and prolog/epilog
+  // insertion.
+  if (PrintMachineCode)
+    PM.add(createMachineFunctionPrinterPass(&std::cerr));
 
+  PM.add(createSparcV8FPMoverPass(*this));
+  PM.add(createSparcV8DelaySlotFillerPass(*this));
+
+  // Print machine instructions after filling delay slots.
+  if (PrintMachineCode)
+    PM.add(createMachineFunctionPrinterPass(&std::cerr));
+
+  // Output assembly language.
+  PM.add(createSparcV8CodePrinterPass(Out, *this));
+
+  // Delete the MachineInstrs we generated, since they're no longer needed.
   PM.add(createMachineCodeDeleter());
   return false;
 }
@@ -61,7 +112,44 @@ bool SparcV8TargetMachine::addPassesToEmitAssembly(PassManager &PM,
 /// implement a fast dynamic compiler for this target.
 ///
 void SparcV8JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
-  // <insert instruction selector passes here>
+  // FIXME: Implement efficient support for garbage collection intrinsics.
+  PM.add(createLowerGCPass());
+
+  // Replace malloc and free instructions with library calls.
+  PM.add(createLowerAllocationsPass());
+  
+  // FIXME: implement the select instruction in the instruction selector.
+  PM.add(createLowerSelectPass());
+  
+  // FIXME: implement the switch instruction in the instruction selector.
+  PM.add(createLowerSwitchPass());
+
+  // FIXME: implement the invoke/unwind instructions!
+  PM.add(createLowerInvokePass());
+
+  PM.add(createLowerConstantExpressionsPass());
+  
+  // Make sure that no unreachable blocks are instruction selected.
+  PM.add(createUnreachableBlockEliminationPass());
+
+  PM.add(createSparcV8SimpleInstructionSelector(TM));
+
+  // Print machine instructions as they were initially generated.
+  if (PrintMachineCode)
+    PM.add(createMachineFunctionPrinterPass(&std::cerr));
+
   PM.add(createRegisterAllocator());
   PM.add(createPrologEpilogCodeInserter());
+
+  // Print machine instructions after register allocation and prolog/epilog
+  // insertion.
+  if (PrintMachineCode)
+    PM.add(createMachineFunctionPrinterPass(&std::cerr));
+
+  PM.add(createSparcV8FPMoverPass(TM));
+  PM.add(createSparcV8DelaySlotFillerPass(TM));
+
+  // Print machine instructions after filling delay slots.
+  if (PrintMachineCode)
+    PM.add(createMachineFunctionPrinterPass(&std::cerr));
 }